• 한국전기전자재료학회:학술대회논문집
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• 한국전기전자재료학회 2009년도 추계학술대회 논문집
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• pp.36-36
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• 2009

In this work, we describe a method to fabricate the Pt-silicided SB-MOSFETs with a n-type Silicon-On-Insulator (SOI) substrate as an active layer and demonstrate their electrical and structural properties. The fabricated SB-MOSFETs have novel structure and metal gate without sidewall. The gate oxide with a thickness of 7 nm was deposited by sputtering. Also, this fabrication processes were carried out below $500^{\circ}C$. As a result, Subthreshold swing value and on/off ratio of Fabricated SB MOSFETs was 70 [mV/dec] and $10^8$.

• 대한기계학회논문집B
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• 제23권8호
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• pp.987-996
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• 1999

An algorithm for modeling the filling of metal into a mold and solidification has been developed. This algorithm uses the implicit VOF method for a filling and a general implicit source-based method for solidification. The model for simultaneous filling and solidification is applied to the two-dimensional filling and solidification of a square cavity. The effects of the wall temperature and gate position on the solidification are examined. The mixed natural convection flow and residual flow resulting from the completion of a filling are included in this study to investigate the coupled effects of the filling and natural convection on solidification. Two different filling configurations (assisting flow and opposite flow due to the gate position) are analysed to study the effects of residual flow on solidification. The results clearly show the necessity to carry out a coupled filling and solidification analysis including the effect of natural convection.

• Journal of information and communication convergence engineering
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• 제10권2호
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• pp.194-199
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• 2012

This paper proposes a novel scheme of a gray scale fingerprint image for a high-accuracy capacitive sensor chip. The conventional grayscale image scheme uses a digital-to-analog converter (DAC) of a large-scale layout or charge-pump circuit with high power consumption and complexity by a global clock signal. A modified capacitive detection circuit for the charge sharing scheme is proposed, which uses a down literal circuit (DLC) with a floating-gate metal-oxide semiconductor transistor (FGMOS) based on a neuron model. The detection circuit is designed and simulated in a 3.3 V, 0.35 ${\mu}m$ standard CMOS process. Because the proposed circuit does not need a comparator and peripheral circuits, the pixel layout size can be reduced and the image resolution can be improved.

• 한국정보디스플레이학회:학술대회논문집
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• 한국정보디스플레이학회 2007년도 7th International Meeting on Information Display 제7권1호
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• pp.958-961
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• 2007

The electrical characteristics of organic thin-filmtransistor (OTFTs) can be improved by inserting adhesion layer on gate dielectrics. Adhesion layer was used as polymeric adhesion layer deposited on inorganic gate insulators such as silicon dioxide $(SiO_2)$ and it was formed by vapor deposition polymerization (VDP) instead of spin-coating process. The OTFTs obtained the on/off ratio $of{\sim}10^4$, threshold voltage of 1.8V, subthreshold slop of 2.9 V/decade and field effect mobility about $0.01\;cm^2/Vs$.

• ETRI Journal
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• 제43권4호
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• pp.728-745
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• 2021

Carbon nanotube field-effect transistors (CNTFETs) have been widely studied as a promising technology to be included in post-complementary metal-oxide-semiconductor integrated circuits. Despite significant advantages in terms of delay and power dissipation, the fabrication process for CNTFETs is plagued by fault occurrences. Therefore, developing a fast and accurate method for estimating the reliability of CNTFET-based digital circuits was the main goal of this study. In the proposed method, effects related to faults that occur in a gate's transistors are first represented as a probability transfer matrix. Next, the target circuit's graph is traversed in topological order and the reliabilities of the circuit's gates are computed. The accuracy of this method (less than 3% reliability estimation error) was verified through various simulations on the ISCAS 85 benchmark circuits. The proposed method outperforms previous methods in terms of both accuracy and computational complexity.

• 열처리공학회지
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• 제22권2호
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• pp.95-100
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• 2009

In this study, the casting process using forged insert was investigated to characterize the manufacturing process by which good mechanical properties can be obtained when compared with existing casting products. Process analysis for the casting design was performed by using FVM (Finite Volume Method) software. In pouring process, three kinds of candidate gating systems are considered and analyzed respectively. The molten metal behavior in gating system is so important that it affects the solidification behavior of the cast. The results show that as the number of gates is increased, hardness of cast was increased and gaps of cast with forged insert were decreased.

• Design & Manufacturing
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• 제14권1호
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• pp.1-7
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• 2020

In this study, the variation of the shrinkage in the thickness direction of the molded parts according to the gate size of the polymer core fabricated through the 3D printer using the SLS method was studied. The polymer cores are laser sintered and the powder material is nylon base PA2200. The polymer cores have lower heat transfer rate and rigidity than the metal core due to the characteristics of the material. Therefore, the injection molding test conditions are set to minimize the deformation of the core during the injection process. The resin used in the injection molding test is a PP material. The packing condition was set to 80, 90 and 100% of the maximum injection pressure for each gate size. The runner diameter used was ∅3mm, and the gates were fabricated in semicircle shapes with cross sections 1, 2, and 3 ㎟, respectively. Thickness measurement was performed for 10 points at 2.5 mm intervals from the point 2.5 mm away from the gate, and the shrinkage to thickness was measured for each point. The shrinkage rate according to the gate size tends to decrease as the cross-sectional area decreases as the maximum injection pressure increases. The average thickness shrinkage rate was close to 0% when the packing pressure was 90% for the gate area of 1mm2. When the holding pressure was set to 100%, the shrinkage was found to decrease by 3% from the standard dimension due to the over-packing phenomenon. Therefore, the smaller the gate, the more closely the molded dimensions can be molded due to the high pressure generation. It was confirmed that precise packing process control is necessary because over-packing phenomenon may occur.

• 한국전자파학회:학술대회논문집
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• 한국전자파학회 2003년도 종합학술발표회 논문집 Vol.13 No.1
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• pp.234-238
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• 2003

In this work, we have designed a fully integrated 2.4GHz LC-tuned voltage-controlled oscillator (VCO) with multiple tuning inputs for a $0.25-{\mu}m$ standard CMOS Process. The design of voltage-controlled oscillator is based on an LC-resonator with a spiral inductor of octagonal type and pMOS-varactors. Only two metal layer have been used in the designed inductor. The frequency tuning is achieved by using parallel pMOS transistors as varactors and back-gate tuned pMOS transistors in an active region. Coarse tuning is achieved by using 3-bit pMOS-varactors and fine tuning is performed by using back-gate tuned pMOS transistors in the active region. When 3-bit digital and analog inputs are applied to the designed circuits, voltage-controlled oscillator shows the tuning feature of frequency range between 2.3 GHz and 2.64 GHz. At the power supply voltage of 2.5 V, phase noise is -128dBc/Hz at 3MHz offset from the carrier, Total power dissipation is 7.5 mW.

• 대한전자공학회:학술대회논문집
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• 대한전자공학회 2003년도 통신소사이어티 추계학술대회논문집
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• pp.32-36
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• 2003

In this work, we have designed a fully integrated 2.4GHz LC-tuned voltage-controlled oscillator (VCO) with multiple tuning inputs for a 0.25-$\mu\textrm{m}$ standard CMOS process. The design of voltage-controlled oscillator is based on an LC-resonator with a spiral inductor of octagonal type and pMOS-varactors. Only two metal layer have been used in the designed inductor. The frequency tuning is achieved by using parallel pMOS transistors as varactors and back-gate tuned pMOS transistors in an active region. Coarse tuning is achieved by using 3-bit pMOS-varactors and fine tuning is performed by using back-gate tuned pMOS transistors in the active region. When 3-bit digital and analog inputs are applied to the designed circuits, voltage-controlled oscillator shows the tuning feature of frequency range between 2.3 GHz and 2.64 GHz. At the power supply voltage of 2.5 V, phase noise is -128dBc/Hz at 3MHz offset from the carrier. Total power dissipation is 7.5 mW.

• 한국정보통신학회:학술대회논문집
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• 한국정보통신학회 2022년도 추계학술대회
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• pp.118-120
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• 2022

본 논문은 M3D(Monolithic 3-Dimension) Inverter의 소자 구조에서 메탈 게이트의 WFV(Work-function Variation)의 영향에 따른 임계전압의 변화에 대하여 조사했다. 또한 PMOS 위에 NMOS가 적층된 인버터의 전기적 상호작용에 따른 임계전압의 변화를 조사하기 위해 PMOS에 0과 1 V의 전압을 인가하여 전기적 상호작용을 조사하였다. 사용된 메탈 게이트의 평균 일함수에 대한 임계전압의 변화량은 0.1684 V로 측정되었고, 표준편차는 0.00079 V가 조사 되었다.