• Journal of IKEEE
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• v.25 no.4
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• pp.778-781
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• 2021

In this paper, we propose the 16-layer 3D NAND Flash memory compact modeling using SPICE. In the same structure and simulation conditions, the channel potential about Down Coupling Phenomenon(DCP) and Natural Local Self Boosting (NLSB) were simulated and analyzed with Technology Computer Aided Design(TCAD) tool Atlas(Silvaco^TM) and SPICE, respectively. As a result, it was confirmed that the channel potential of TCAD and SPICE for the two phenomena were almost same. The SPICE can be checked the device structure intuitively by using netlist. Also, its simulation time is shorter than TCAD. Therefore, using SPICE can be expected to efficient research on 3D NAND Flash memory.

• Journal of the Institute of Electronics Engineers of Korea SD
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• v.44 no.12
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• pp.85-92
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• 2007

With the development of the memory design and process technology, the production of high-density memory has become a large scale industry. Since these memories require complicated designs and accurate manufacturing processes, It is possible to exist more defects. Therefore, in order to analyze the defects, repair them and fix the problems in the manufacturing process, memory repair using BISR(Built-In Self-Repair) circuit is recently focused. This paper presents an efficient memory BISR architecture that uses spare memories effectively. The proposed BISR architecture utilizes the additional storage space named 'sign bit' for the repair of memories. This shows the better performance compared with the previous works.

• Journal of the Institute of Electronics Engineers of Korea SD
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• v.45 no.2
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• pp.69-81
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• 2008

The density of Memory has been increased by great challenge for memory technology, so elements of memory become smaller than before and the sensitivity to faults increases. As a result of these changes, memory testing becomes more complex. The number of storage elements is increased per chip, and the cost of test becomes more remarkable as the cost per transistor drops. Proposed design doesn't need to control from outside environment, because it integrates into memory. The proposed scheme supports the various memory testing algorithms. Consequently, the proposed one is more efficient in terms of test cost and test data to be applied. Moreover, we proposed a reallocation algorithm for faulty memory parts. It has an efficient reallocation scheme with row and column redundant memory. Previous reallocation information is obtained from faulty memory every each tests. However proposed scheme avoids to this problem. because onetime test result from reallocation information can save to flash memory. In this paper, a reallocation scheme has been increased efficiency because of using flash memory.

• Proceedings of the Computational Structural Engineering Institute Conference
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• 2006.04a
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• pp.291-298
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• 2006

A parallelized topology design optimization method is developed on a distributed memory system. The parallelization is based on a domain decomposition method and a boundary communication scheme. For the finite element analysis of structural responses and design sensitivities, the PCG method based on a Krylov iterative scheme is employed. Also a parallelized optimization method of optimality criteria is used to solve large-scale topology optimization problems. Through several numerical examples, the developed method shows efficient and acceptable topology optimization results for the large-scale problems.

• The Journal of Korean Institute of Communications and Information Sciences
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• v.35 no.6B
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• pp.984-990
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• 2010

In Current Digital $C^3$ Devices(Communication, Computer, Consumer electronic devices), Reed-Solomon encoder is essentially used. For example we should use RS encoder in DSP LSI of CDMA Mobile and Base station modem, in controller LSI of DVD Recorder and that of computer memory(HDD or SSD memory). In this paper, we propose new economical multiplierless (also without divider) RS encoder design method. The encoder has Arbitrary parity positions.

• Proceedings of the Korean Institute of Intelligent Systems Conference
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• 1995.10b
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• pp.264-272
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• 1995

This paper presents an efficient design method to realize an associative memory with BSB neural networks by means of the parametrization of the solution space and searching for the optimal solution using an evolution program. In particular, the performance index based on DOA analysis in this paper may make and associative memory implementation to reach on the level of practical success.

• Proceedings of the IEEK Conference
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• 2003.07c
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• pp.2637-2640
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• 2003

In this paper, we propose a simple and efficient data input/output block with high speed between Motorola MPC8XX microprocessor and memory devices. Proposed method is capable of high speed data read and write using the address decoder and the burst cycle between Motorola PowerPC based MPC8XX microprocessor and fixed address locating memory devices such as FIFO, PCMCIA card, and so on. Experimental results are given our findings and discussions.

• 한국정보디스플레이학회:학술대회논문집
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• 2007.08a
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• pp.806-809
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• 2007

SRAM cell array and peripheral circuits on display panel are designed using LTPS process. To overcome low yield of SOP, high speed parallel fault detection circuitry for memory cells is designed at local I/O lines with minimal overhead for efficient memory cell redundancy replacement. Normal read/write and parallel test read/write are simulated and verified.

• Journal of KIISE:Computing Practices and Letters
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• v.15 no.1
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• pp.1-13
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• 2009

Flash memory is widely used as a storage medium of mobile devices such as MP3 players, cellular phones and digital cameras due to its tiny size, low power consumption and shock resistant characteristics. Currently, there are many studies to replace HDD with flash memory because of its numerous strong points. To use flash memory as a storage medium, FTL(Flash Translation Layer) is required since flash memory has erase-before-write constraints and sizes of read/write unit and erase unit are different from each other. Recently, new type of flash memory called "large block flash memory" is introduced. The large block flash memory has different physical structure and characteristics from previous flash memory. So existing FTLs are not efficiently operated on large block flash memory. In this paper, we propose an efficient FTL for large block flash memory based on FAST(Fully Associative Sector Translation) scheme and page-level mapping on data blocks.

• 제어로봇시스템학회:학술대회논문집
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• 2003.10a
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• pp.1767-1770
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• 2003

This paper proposes an efficient network architecture for reflective memory system (RMS). Using this architecture, the time for broadcasting a shared-data to all nodes can be significantly shortened. The device named topology conversion switch (TCS) is implemented to realize the network architecture. The implemented TCS is applied to the ethernet based real time control network (ERCnet) to evaluate the performance.