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The Efficient Memory BISR Architecture using Sign Bits  

Kang, Il-Kwon (Department of Electrical and Electronic Engineering, Yonsei University)
Kang, Sung-Ho (Department of Electrical and Electronic Engineering, Yonsei University)
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Abstract
With the development of the memory design and process technology, the production of high-density memory has become a large scale industry. Since these memories require complicated designs and accurate manufacturing processes, It is possible to exist more defects. Therefore, in order to analyze the defects, repair them and fix the problems in the manufacturing process, memory repair using BISR(Built-In Self-Repair) circuit is recently focused. This paper presents an efficient memory BISR architecture that uses spare memories effectively. The proposed BISR architecture utilizes the additional storage space named 'sign bit' for the repair of memories. This shows the better performance compared with the previous works.
Keywords
memory repair; memory BISR; BIRA; self-repair;
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1 S. Hamdioui, G. Gaydadjiev and Ad J. van de Goor, 'The State-of-art and Future Trends in Testing Embedded Memories', Record of the 2004 International Workshop on Memory Technology, Design and Testing, pp. 54-59, August 2004
2 M. Tarr, D. Boudreau, and R. Murphy, 'Defect analysis system speeds test and repair of redundant memories', Electron, pp. 175-179, Jan. 1984
3 T. Chen and G. Sunada, 'Design Self-Testing and Self-Repairing Structure for High Hierarchical Ultra-Large Capacity Memory Chips', IEEE Trans. On VLSI, Vol. 1, No. 2, pp. 86-95, 1995
4 D. K. Bhavsar, 'An Algorithm for Row-Column Self-Repair of RAMs and Its Implementation in the Alpha 21264', In Proc. of ITC, pp. 311-317. 1999
5 T. Kawagoe, et. al, 'A Built-in Self-Repair Analyzer (CRESTA) for embedded DRAMs', In Proc. of ITC, pp. 567-573, 2000
6 J. F. Li, J. C. Yeh, R. F. Huang and C. H. Wu, 'A Built-In Self-Repair Design for RAMs With 2-D Redundancy', IEEE Trans. On VLSI, Vol. 13, No. 6, pp. 742-745, June 2005   DOI   ScienceOn
7 R. Rajsuman, 'Design and test of large embedded memories : An overview', IEEE Design Test Comput., Vol. 18, No. 3, pp. 16-27, May 2001