1 |
S. Hamdioui, G. Gaydadjiev and Ad J. van de Goor, 'The State-of-art and Future Trends in Testing Embedded Memories', Record of the 2004 International Workshop on Memory Technology, Design and Testing, pp. 54-59, August 2004
|
2 |
M. Tarr, D. Boudreau, and R. Murphy, 'Defect analysis system speeds test and repair of redundant memories', Electron, pp. 175-179, Jan. 1984
|
3 |
T. Chen and G. Sunada, 'Design Self-Testing and Self-Repairing Structure for High Hierarchical Ultra-Large Capacity Memory Chips', IEEE Trans. On VLSI, Vol. 1, No. 2, pp. 86-95, 1995
|
4 |
D. K. Bhavsar, 'An Algorithm for Row-Column Self-Repair of RAMs and Its Implementation in the Alpha 21264', In Proc. of ITC, pp. 311-317. 1999
|
5 |
T. Kawagoe, et. al, 'A Built-in Self-Repair Analyzer (CRESTA) for embedded DRAMs', In Proc. of ITC, pp. 567-573, 2000
|
6 |
J. F. Li, J. C. Yeh, R. F. Huang and C. H. Wu, 'A Built-In Self-Repair Design for RAMs With 2-D Redundancy', IEEE Trans. On VLSI, Vol. 13, No. 6, pp. 742-745, June 2005
DOI
ScienceOn
|
7 |
R. Rajsuman, 'Design and test of large embedded memories : An overview', IEEE Design Test Comput., Vol. 18, No. 3, pp. 16-27, May 2001
|