• JSTS:Journal of Semiconductor Technology and Science
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• v.17 no.3
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• pp.363-369
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• 2017

Phase-change random access memory (PRAM) has been emerged as a potential memory due to its excellent scalability, non-volatility, and random accessibility. But, as the cell current is reducing due to cell size scaling, the read-sensing window margin is also decreasing due to increased variation of cell performance distribution, resulting in a substantial loss of yield. To cope with this problem, a novel adaptive read-sensing reference current generation scheme is proposed, whose trimming range and resolution are adaptively controlled depending on process conditions. Performance evaluation in a 58-nm CMOS process indicated that the proposed read-sensing reference current scheme allowed the integral nonlinearity (INL) to be improved from 10.3 LSB to 2.14 LSB (79% reduction), and the differential nonlinearity (DNL) from 2.29 LSB to 0.94 LSB (59% reduction).

• Journal of Mechanical Science and Technology
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• v.18 no.3
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• pp.453-459
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• 2004

TiNi/ Al6061 shape memory alloy (SMA) composite was fabricated by hot press method to investigate the microstructure and mechanical properties. Interface bonding between TiNi reinforcement and A1 matrix was observed by using SEM and EDS. Pre-strain was imposed to generate compressive residual stress inside composite. A tensile test for specimen, which under-went pre-strain, was performed at high temperature to evaluate the variation of strength and the effect of pre-strain. It was shown that interfacial reactions occurred at the bonding between matrix and fiber, creating two inter-metallic layers. And yield stress increased with the amount of pre-strain. Acoustic Emission technique was also used to nondestructively clarify the microscopic damage behavior at high temperature and the effect of pre-strain of TiNi/ Al6061 SMA composite.

• Journal of Urban Science
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• v.11 no.1
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• pp.1-8
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• 2022

As the magnitude and frequency of earthquakes increase in Korea, interest in earthquake damage reduction technology has increased. Therefore, research on vibration damping devices that directly respond to seismic loads is being actively researched. After an earthquake, damage or destruction of the device occurs due to the yield of materials, and thus it takes considerable cost and time for restoration and replacement. To supplement the problems of the existing earthquake damage reduction technology, a study was conducted on the recentering smart damper that can be used continuously after an earthquake. In this study, the recentering smart damper that can be restored to its original shape after load removal was developed using superelastic shape memory alloy, pre-compressed polyurethane. General steel was commonly applied to verify the seismic performance of the superelastic shape memory alloy, and the performance of the smart damper was verified according to the amount of polyurethane pre-compressed

• Journal of the Korean Society for Heat Treatment
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• v.3 no.1
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• pp.34-41
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• 1990

Effects of grain size and cold rolling degree on shape memory ability and transformation temperature were studied in Fe-35% Mn-6% Si shape memory alloy. Md point of the alloy was determined by variation of yield stress with test temperature. The Md point measured in this way was linearly increased with increasing grain size. Shape memory ability of the alloy was decreased with increasing grain size, showing a minimum value at around $63{\mu}m$, and then increased with increasing grain size. From this result, it was concluded that the shape memory ability in the grain size smaller than a critical value is controlled by amount of retained ${\gamma}$ and prior ${\varepsilon}$ phase, but that the shape memory ability in the grain size greater than the critical value is mainly dominated by grain boundary area in unit volume of parent phase. The shape memory ability was decreased with increasing deformation degree. This was because the ${\gamma}$ content being available for the formation of ${\varepsilon}$ martensite during bending was decreased with increasing deformation degree.

• Composites Research
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• v.17 no.5
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• pp.54-60
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• 2004

A new three-dimensional model for predicting the relationship between the prestrain of the composite and the amount of phase transformation of shape memory alloy inducing shape memory effect has been proposed by using Eshelby's equivalent inclusion method with Mori-Tanaka's mean field theory. The model composite is aluminum matrix reinforced with short TiNi fiber shape memory alloy, where the matrix is work-hardening material of power-law type. The analytical results predicted by the current model show that most of the prestrain is induced by the plastic deformation of the matrix, except the small prestrain region. The strengthening mechanism of the composite by the shape memory effect should be explained by excluding its increase of yield stress due to the work-hardening effect of the matrix.

• Journal of the Institute of Electronics and Information Engineers
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• v.50 no.2
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• pp.114-121
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• 2013

As the weight of embedded memory within Systems-On-Chips(SoC) rapidly increases to 80-90% of the number of total transistors, the importance of testing embedded memory in SoC increases. This paper proposes IEEE std. 1500 wrapper based Programmable Memory Built-In Self-Test(PMBIST) architecture which can support various kinds of test algorithm. The proposed PMBIST guarantees high flexibility, programmability and fault coverage using not only March algorithms but also non-March algorithms such as Walking and Galloping. The PMBIST has an optimal hardware overhead by an optimum program instruction set and a smaller program memory. Furthermore, the proposed fault information processing scheme guarantees improvement of the memory yield by effectively supporting three types of the diagnostic methods for repair and diagnosis.

• JSTS:Journal of Semiconductor Technology and Science
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• v.4 no.1
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• pp.45-51
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• 2004

We have proposed a new shallow trench isolation (STI) process using flowable oxide (F-oxide) chemical vapor deposition (CVD) for DRAM application and it was successfully developed. The combination of F-oxide CVD and HDP CVD is thought to be the superior STI gap-filling process for next generation DRAM fabrication because F-oxide not only improves STI gap-filling capability, but also the reduced local stress by F-oxide in narrow trenches leads to decrease in junction leakage and gate induced drain leakage (GIDL) current. Finally, this process increased data retention time of DRAM compared to HDP STI. However, a serious failure occurred by symphonizing its structural dependency of deposited thickness with poor resistance against HF chemicals. It could be suppressed by reducing the flow time during F-oxide deposition. It was investigated collectively in terms of device yield. In conclusion, the combination of F-oxide and HDP oxide is the very promising technology for STI gap filling process of sub-100nm DRAM technology.

• Journal of the Institute of Electronics Engineers of Korea SD
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• v.40 no.1
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• pp.72-79
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• 2003

Due to the improvements in circuit design technique and manufacturing technique, complexity of a circuit is growing along with the demand for memories with large capacities. Likewise, as a memory capacity gets larger, testing gets harder and testing cost increases, and testing process in chip development gets larger as well. Therefore, a research on an effective test algorithm to improve the chip yield rate in a short time period is becoming an important task. This paper proposes an effective, March C-algorithm based, test algorithm that can also be applied to a dual-port memory since it considers all the fault types, which can be occurred in a single-port as well as in a dual-port memory, without increasing the test length.

• Journal of the Korea Institute of Information and Communication Engineering
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• v.14 no.11
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• pp.2541-2547
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• 2010

In this paper, we propose a design technique which replaces logic transistors of 1.2V with medium-voltage transistors of 3.3V having small off-leakage current in repetitive block circuits where speed is not an issue, to implement a low-power eFuse OTP memory IP in the stand-by state. In addition, we use dual-port eFuse cells reducing operational current dissipation by reducing capacitances parasitic to RWL (Read word-line) and BL (Bit-line) in the read mode. Furthermore, we propose an equivalent circuit for simulating program power injected to an eFuse from a program voltage. The layout size of the designed 512-bit eFuse OTP memory IP with a 90nm CMOS image sensor process is $342{\mu}m{\times}236{\mu}m$. It is confirmed by measurement experiments on 42 samples with a program voltage of 5V that we get a good result having 97.6 percent of program yield. Also, the minimal operational supply voltage is measured well to be 0.9V.

• Journal of the Institute of Electronics Engineers of Korea SD
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• v.47 no.11
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• pp.30-36
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• 2010

In recent memories, repair is an unavoidable method to maintain its yield and quality. Although many word oriented memories as well as embedded memories in system-on-chip (SOC) consists of multiple local memory blocks with a global spare architecture, most of previous studies on built-in redundancy analysis (BIRA) algorithms have focused on single memory block with a local spare architecture. In this paper, a new BIRA algorithm for multiple blocks with a global spare architecture is proposed. The proposed BIRA is basd on CRESTA which is able to achieve optimal repair rate with almost zero analysis time. In the proposed BIRA, all repair solutions for local memory blocks are analyzed by local analyzers which belong to each local memory block and then compared sequentially and judged whether each solution can meet the limitation of the global spare architecture or not. Experimental results show that the proposed BIRA achieves much faster analysis speed compared to previous BIRAs with an optimal repair rate.