• 아태비즈니스연구
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• 제11권4호
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• pp.255-269
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• 2020

Purpose - This paper analyzes the market efficiency focusing on the long memory properties of the domestic futures market. By decomposing futures prices into yield and volatility and looking at the long memory properties of the time series, this study aims to understand the futures market pricing and change behavior and risks, specifically and in detail. Design/methodology/approach - This study analyzes KOSPI 200 futures, KOSDAQ 150 futures, 3 and 10-year government bond futures, US dollar futures, yen futures, and euro futures, which are among the most actively traded on the Korea Exchange. To analyze the long memory and market efficiency, we used the Variance Ratio, Rescaled-Range(R/S), Geweke and Porter-Hudak(GPH) tests as semi- parametric methods, and ARFIMA-FIGARCH model as the parametric method. Findings - It was found that all seven futures supported the efficiency market hypothesis because the property of long memory turned out not to exist in their yield curves. On the other hand, in futures volatility, all 7 futures showed long memory properties in the analysis, which means that if new information is generated in the domestic futures market and the market volatility once expanded due to the impact, it does not decrease or shrink for a long period of time, but continues to affect the volatility. Research implications or Originality - The results of this paper suggest that it can be useful information for predicting changes and risks of volatility in the domestic futures market. In particular, it was found that the long memory properties would be further strengthened in the currency futures and bond rate futures markets after the global financial crisis if the regime changes of the domestic financial market are taken into account in the analysis.

• 전자공학회논문지
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• 제49권9호
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• pp.237-243
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• 2012

최근의 시스템 온 칩 (SoC) 설계 기술의 발전에 따라, 수백개의 임베디드 메모리 코어들이 칩의 대부분의 면적을 차지하고 있다. 그러므로 시스템 온 칩의 수율은 임베디드 메모리 코어들의 수율에 따라 결정된다고 볼 수 있다. 최적의 수리 효율을 가지는 built-in self repair (BISR)을 모든 메모리들이 가지고 있게 된다면 면적의 부담이 너무 크다. 본 논문에서는 이와 같은 면적의 부담을 줄이기 위하여 메모리들을 그룹화 한 후에 비트맵 메모리를 공유하여 면적 부담을 크게 줄이는 방법을 제안한다. 제안하는 비트맵 메모리 공유방법은 built-in redundancy analysis (BIRA)의 면적을 크게 줄일 수 있다. 실험결과를 통해서 보면 제안하는 방법이 면적 부담을 대략 80%정도 줄이는 것을 확인 할 수 있다.

• 대한기계학회논문집A
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• 제26권7호
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• pp.1223-1231
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• 2002

Al alloy matrix composite with TiNi shape memory fiber as reinforcement has been fabricated by hot pressing to investigate microstructures and mechanical properties. The analysis of SEM and EDS showed that the composites have shown good interface bonding. The stress-strain behavior of the composites was evaluated at temperatures between 363K and room temperature as a function of prestrain, and it showed that the yield stress at 363K was higher than that of the room temperature. Especially, the yield stress of this composite increases with increasing the amount of prestrain, and it also depends on the volume fraction of fiber and heat treatment. The smartness of the composite is given due to the shape memory effect of the TiNi fiber which generates compressive residual stress in the matrix material when heated after being prestrained. Microstructural observation has revealed that interfacial reactions occur between the matrix and fiber, creating two intermetallic layers.

• 한국정보디스플레이학회:학술대회논문집
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• 한국정보디스플레이학회 2007년도 7th International Meeting on Information Display 제7권1호
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• pp.806-809
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• 2007

SRAM cell array and peripheral circuits on display panel are designed using LTPS process. To overcome low yield of SOP, high speed parallel fault detection circuitry for memory cells is designed at local I/O lines with minimal overhead for efficient memory cell redundancy replacement. Normal read/write and parallel test read/write are simulated and verified.

• 한국정보통신학회:학술대회논문집
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• 한국해양정보통신학회 2011년도 춘계학술대회
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• pp.687-691
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• 2011

본 논문에서는 아날로그 트리밍용으로 사용되는 $0.18{\mu}m$ generic 공정 기반의 EM(Electro-Migration)과 eFuse의 저항 변동을 고려한 8bit eFuse OTP (One-Time Programmable) 메모리를 설계하였다. eFuse OTP 메모리는 eFuse에 인가되는 program power를 증가시키기 위해 external program voltage를 사용하였으며, 프로그램되지 않은 cell에 흐르는 read current를 낮추기 위해 RWL (Read Word-Line) activation 이전에 BL을 VSS로 precharging하는 방식과 read NMOS transistor를 최적화 설계하였다. 그리고 프로그램된 eFuse 저항의 변동을 고려한 variable pull-up load를 갖는 sensing margin test 회로를 설계하였다. 한편 eFuse link의 length를 split하여 eFuse OTP의 프로그램 수율 (program yield)을 높였다.

• ETRI Journal
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• 제34권3호
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• pp.478-481
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• 2012

Testing memory and repairing faults have become increasingly important for improving yield. Redundancy analysis (RA) algorithms have been developed to repair memory faults. However, many RA algorithms have low analysis speeds and occupy memory space within automatic test equipment. A fast RA algorithm using simple calculations is proposed in this letter to minimize both the test and repair time. This analysis uses the grouped addresses in the faulty bitmap. Since the fault groups are independent of each other, the time needed to find solutions can be greatly reduced using these fault groups. Also, the proposed algorithm does not need to store searching trees, thereby minimizing the required memory space. Our experiments show that the proposed RA algorithm is very efficient in terms of speed and memory requirements.

• 정보처리학회논문지:컴퓨터 및 통신 시스템
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• 제3권5호
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• pp.129-140
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• 2014

기존의 메모리에서 발생하는 다양한 고장들을 검출하기 위한 기법으로 BIST(Built-in self test)가 있고 고장이 검출되면 Spare를 할당하여 수리하는 BIRA(Built-in redundancy analysis)가 있다. 그리고 BIST와 BIRA를 통합한 형태인 BISR(Built-in self repair)를 통해 전체 메모리의 수율을 증가시킬 수 있다. 그러나 이전에 제안된 기법들은 RAM을 위해 제안된 기법으로 RAM의 메모리 구조와 특성이 다른 NAND-형 플래시 메모리에 사용하기에는 NAND-형 플래시 메모리의 고유 고장인 Disturbance를 진단하기 어렵다. 따라서 본 논문에서는 NAND-형 플래시 메모리에서 발생하는 Disturbance 고장을 검출하고 고장의 위치도 진단할 있는 BISD(Built-in self diagnosis)와 고장 블록을 수리할 수 있는 BISR을 제안한다.

• JSTS:Journal of Semiconductor Technology and Science
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• 제1권4호
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• pp.216-231
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• 2001

Several methods for improving device yields and characteristics have been studied by IC manufacturers, as the options for programming components become diversified through the introduction of novel processes. Especially, the sequential repair steps on wafer level and package level are essentially required in DRAMs to improve the yield. Several repair methods for DRAMs are reviewed in this paper. They include the optical methods (laser-fuse, laser-antifuse) and the electrical methods (electrical-fuse, ONO-antifuse). Theses methods can also be categorized into the wafer-level(on wafer) and the package-level(post-package) repair methods. Although the wafer-level laser-fuse repair method is the most widely used up to now, the package-level antifuse repair method is becoming an essential auxiliary technique for its advantage in terms of cost and design efficiency. The advantages of the package-level antifuse method are discussed in this paper with the measured data of manufactured devices. With devices based on several processes, it was verified that the antifuse repair method can improve the net yield by more than 2%~3%. Finally, as an illustration of the usefulness of the package-level antifuse repair method, the repair method was applied to the replica delay circuit of DLL to get the decrease of clock skew from 55ps to 9ps.

• Smart Structures and Systems
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• 제15권3호
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• pp.897-911
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• 2015

This study presents a novel approach based on advancements in Evolutionary Computation for data-driven modeling of complex multi-dimensional memory-dependent systems. The investigated example is a benchmark coupled three-dimensional system that incorporates 6 Bouc-Wen elements, and is subjected to external excitations at three points. The proposed technique of this research adapts Genetic Programming for discovering the optimum structure of the differential equation of an auxiliary variable associated with every specific degree-of-freedom of this system that integrates the imposed effect of vibrations at all other degrees-of-freedom. After the termination of the first phase of the optimization process, a system of differential equations is formed that represent the multi-dimensional hysteretic system. Then, the parameters of this system of differential equations are optimized in the second phase using Genetic Algorithms to yield accurate response estimates globally, because the separately obtained differential equations are coupled essentially, and their true performance can be assessed only when the entire system of coupled differential equations is solved. The resultant model after the second phase of optimization is a low-order low-complexity surrogate computational model that represents the investigated three-dimensional memory-dependent system. Hence, this research presents a promising data-driven modeling technique for obtaining optimized representative models for multi-dimensional hysteretic systems that yield reasonably accurate results, and can be generalized to many problems, in various fields, ranging from engineering to economics as well as biology.

• ETRI Journal
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• 제35권3호
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• pp.439-447
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• 2013

To increase device memory yield, many manufacturers use incorporated redundancy to replace faulty cells. In this redundancy technology, the implementation of an effective redundancy analysis (RA) algorithm is essential. Various RA algorithms have been developed to repair faults in memory. However, nearly all of these RA algorithms have low analysis speeds. The more densely compacted the memory is, the more testing and repair time is needed. Even if the analysis speed is very high, the RA algorithm would be useless if it did not have a normalized repair rate of 100%. In addition, when the number of added spares is increased in the memory, then the memory space that must be searched with the RA algorithms can exceed the memory space within the automatic test equipment. A very efficient RA algorithm using simple calculations is proposed in this work so as to minimize both the repair time and memory consumption. In addition, the proposed algorithm generates an optimal solution using a tree-based algorithm in each fault group. Our experiment results show that the proposed RA algorithm is very efficient in terms of speed and repair.