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Electronics and Telecommunications Research Institute (한국전자통신연구원)
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A Fast Redundancy Analysis Algorithm in ATE for Repairing Faulty Memories

  • Cho, Hyung-Jun (Department of Electrical & Electronic Engineering, Yonsei University) ;
  • Kang, Woo-Heon (Department of Electrical & Electronic Engineering, Yonsei University) ;
  • Kang, Sung-Ho (Department of Electrical & Electronic Engineering, Yonsei University)
  • Received : 2011.09.02
  • Accepted : 2011.11.03
  • Published : 2012.06.01
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Abstract

Testing memory and repairing faults have become increasingly important for improving yield. Redundancy analysis (RA) algorithms have been developed to repair memory faults. However, many RA algorithms have low analysis speeds and occupy memory space within automatic test equipment. A fast RA algorithm using simple calculations is proposed in this letter to minimize both the test and repair time. This analysis uses the grouped addresses in the faulty bitmap. Since the fault groups are independent of each other, the time needed to find solutions can be greatly reduced using these fault groups. Also, the proposed algorithm does not need to store searching trees, thereby minimizing the required memory space. Our experiments show that the proposed RA algorithm is very efficient in terms of speed and memory requirements.

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References

  1. S.-Y. Kuo and W.K. Fuchs, "Efficient Spare Allocation for Reconfigurable Arrays," IEEE Design Test Computers, vol. 4, no. 1, Feb. 1987, pp. 24-31.
  2. P. Ohler, S. Hellebrand, and H.-J. Wunderlich, "An Integrated Built-in Test and Repair Approach for Memories with 2D Redundancy," Proc. IEEE European Test Symp. (ETS), May 2007, pp. 91-96.
  3. H. Cho, W. Kang, and S. Kang, "A Built-in Redundancy Analysis with a Minimized Binary Search Tree," ETRI J., vol. 32, no. 4, Aug. 2010, pp. 638-641. https://doi.org/10.4218/etrij.10.0210.0032
  4. W. Jeong et al., "An Advanced BIRA for Memories with an Optimal Repair Rate and Fast Analysis Speed by Using a Branch Analyzer," IEEE Trans. CAD, vol. 29, no. 12, Dec. 2010, pp. 2014-2026.
  5. H.-Y. Lin, F.-M. Yeh, and S.-Y. Kuo, "An Efficient Algorithm for Spare Allocation Problems," IEEE Trans. Reliability, vol. 55, no. 2, June 2006, pp. 369-378. https://doi.org/10.1109/TR.2006.874942
  6. C.-T. Huang et al., "Built-in Redundancy Analysis for Memory Yield Improvement," IEEE Trans. Reliability, vol. 52, Dec. 2003, pp. 386-399. https://doi.org/10.1109/TR.2003.821925

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  1. Recovering from Biased Distribution of Faulty Cells in Memory by Reorganizing Replacement Regions through Universal Hashing vol.23, pp.2, 2012, https://doi.org/10.1145/3131241