• Asia-Pacific Journal of Business
• /
• v.11 no.4
• /
• pp.255-269
• /
• 2020

Purpose - This paper analyzes the market efficiency focusing on the long memory properties of the domestic futures market. By decomposing futures prices into yield and volatility and looking at the long memory properties of the time series, this study aims to understand the futures market pricing and change behavior and risks, specifically and in detail. Design/methodology/approach - This study analyzes KOSPI 200 futures, KOSDAQ 150 futures, 3 and 10-year government bond futures, US dollar futures, yen futures, and euro futures, which are among the most actively traded on the Korea Exchange. To analyze the long memory and market efficiency, we used the Variance Ratio, Rescaled-Range(R/S), Geweke and Porter-Hudak(GPH) tests as semi- parametric methods, and ARFIMA-FIGARCH model as the parametric method. Findings - It was found that all seven futures supported the efficiency market hypothesis because the property of long memory turned out not to exist in their yield curves. On the other hand, in futures volatility, all 7 futures showed long memory properties in the analysis, which means that if new information is generated in the domestic futures market and the market volatility once expanded due to the impact, it does not decrease or shrink for a long period of time, but continues to affect the volatility. Research implications or Originality - The results of this paper suggest that it can be useful information for predicting changes and risks of volatility in the domestic futures market. In particular, it was found that the long memory properties would be further strengthened in the currency futures and bond rate futures markets after the global financial crisis if the regime changes of the domestic financial market are taken into account in the analysis.

• Journal of the Institute of Electronics and Information Engineers
• /
• v.49 no.9
• /
• pp.237-243
• /
• 2012

In recent system-on-chip (SoC) designs, several hundred embedded memory cores have occupied the largest portion of the chip area. Therefore, the yield of SoCs is strongly dependent on the yield of the embedded memory cores. If all memories had built-in self repair (BISR) with optimal repair rates, the area overhead would be very large. A bit-map sharing method using a memory grouping is proposed to reduce the area overhead. Since the bit-map memory occupies the largest portion of the area of the built-in redundancy analysis (BIRA), the proposed bit-map sharing method can greatly reduce the area overhead of the BIRA. Based on the experimental results, the proposed method can reduce the area overhead by about 80%.

• Transactions of the Korean Society of Mechanical Engineers A
• /
• v.26 no.7
• /
• pp.1223-1231
• /
• 2002

Al alloy matrix composite with TiNi shape memory fiber as reinforcement has been fabricated by hot pressing to investigate microstructures and mechanical properties. The analysis of SEM and EDS showed that the composites have shown good interface bonding. The stress-strain behavior of the composites was evaluated at temperatures between 363K and room temperature as a function of prestrain, and it showed that the yield stress at 363K was higher than that of the room temperature. Especially, the yield stress of this composite increases with increasing the amount of prestrain, and it also depends on the volume fraction of fiber and heat treatment. The smartness of the composite is given due to the shape memory effect of the TiNi fiber which generates compressive residual stress in the matrix material when heated after being prestrained. Microstructural observation has revealed that interfacial reactions occur between the matrix and fiber, creating two intermetallic layers.

• 한국정보디스플레이학회:학술대회논문집
• /
• 2007.08a
• /
• pp.806-809
• /
• 2007

SRAM cell array and peripheral circuits on display panel are designed using LTPS process. To overcome low yield of SOP, high speed parallel fault detection circuitry for memory cells is designed at local I/O lines with minimal overhead for efficient memory cell redundancy replacement. Normal read/write and parallel test read/write are simulated and verified.

• Proceedings of the Korean Institute of Information and Commucation Sciences Conference
• /
• 2011.05a
• /
• pp.687-691
• /
• 2011

In this paper, we design an 8-bit eSuse OTP (one-time programmable) memory in consideration of EM (electro-migration) and eFuse resistance variation based on a $0.18{\mu}m$ generic process, which is used for an analog trimming application. First, we use an external program voltage to increase the program power applied an eFuse. Secondly, we apply a scheme of precharging BL to VSS prior to RWL (read word line) activation and optimize read NMOS transistors to reduce the read current flowing through a non-programmed cell. Thirdly, we design a sensing margin test circuit with a variable pull-up load out of consideration for the eFuse resistance variation of a programmed eFuse. Finally, we increase program yield of eFuse OTP memory by splitting the length of an eFuse link.

• ETRI Journal
• /
• v.34 no.3
• /
• pp.478-481
• /
• 2012

Testing memory and repairing faults have become increasingly important for improving yield. Redundancy analysis (RA) algorithms have been developed to repair memory faults. However, many RA algorithms have low analysis speeds and occupy memory space within automatic test equipment. A fast RA algorithm using simple calculations is proposed in this letter to minimize both the test and repair time. This analysis uses the grouped addresses in the faulty bitmap. Since the fault groups are independent of each other, the time needed to find solutions can be greatly reduced using these fault groups. Also, the proposed algorithm does not need to store searching trees, thereby minimizing the required memory space. Our experiments show that the proposed RA algorithm is very efficient in terms of speed and memory requirements.

• KIPS Transactions on Computer and Communication Systems
• /
• v.3 no.5
• /
• pp.129-140
• /
• 2014

BIST(Built-in self test) is to detect various faults of the existing memory and BIRA(Built-in redundancy analysis) is to repair detected faults by allotting spare. Also, BISR(Built-in self repair) which integrates BIST with BIRA, can enhance the whole memory's yield. However, the previous methods were suggested for RAM and are difficult to diagnose disturbance that is NAND-type flash memory's intrinsic fault when used for the NAND-type flash memory with different characteristics from RAM's memory structure. Therefore, this paper suggests a BISD(Built-in self diagnosis) to detect disturbance occurring in the NAND-type flash memory and to diagnose the location of fault, and BISR to repair faulty blocks.

• JSTS:Journal of Semiconductor Technology and Science
• /
• v.1 no.4
• /
• pp.216-231
• /
• 2001

Several methods for improving device yields and characteristics have been studied by IC manufacturers, as the options for programming components become diversified through the introduction of novel processes. Especially, the sequential repair steps on wafer level and package level are essentially required in DRAMs to improve the yield. Several repair methods for DRAMs are reviewed in this paper. They include the optical methods (laser-fuse, laser-antifuse) and the electrical methods (electrical-fuse, ONO-antifuse). Theses methods can also be categorized into the wafer-level(on wafer) and the package-level(post-package) repair methods. Although the wafer-level laser-fuse repair method is the most widely used up to now, the package-level antifuse repair method is becoming an essential auxiliary technique for its advantage in terms of cost and design efficiency. The advantages of the package-level antifuse method are discussed in this paper with the measured data of manufactured devices. With devices based on several processes, it was verified that the antifuse repair method can improve the net yield by more than 2%~3%. Finally, as an illustration of the usefulness of the package-level antifuse repair method, the repair method was applied to the replica delay circuit of DLL to get the decrease of clock skew from 55ps to 9ps.

• Smart Structures and Systems
• /
• v.15 no.3
• /
• pp.897-911
• /
• 2015

This study presents a novel approach based on advancements in Evolutionary Computation for data-driven modeling of complex multi-dimensional memory-dependent systems. The investigated example is a benchmark coupled three-dimensional system that incorporates 6 Bouc-Wen elements, and is subjected to external excitations at three points. The proposed technique of this research adapts Genetic Programming for discovering the optimum structure of the differential equation of an auxiliary variable associated with every specific degree-of-freedom of this system that integrates the imposed effect of vibrations at all other degrees-of-freedom. After the termination of the first phase of the optimization process, a system of differential equations is formed that represent the multi-dimensional hysteretic system. Then, the parameters of this system of differential equations are optimized in the second phase using Genetic Algorithms to yield accurate response estimates globally, because the separately obtained differential equations are coupled essentially, and their true performance can be assessed only when the entire system of coupled differential equations is solved. The resultant model after the second phase of optimization is a low-order low-complexity surrogate computational model that represents the investigated three-dimensional memory-dependent system. Hence, this research presents a promising data-driven modeling technique for obtaining optimized representative models for multi-dimensional hysteretic systems that yield reasonably accurate results, and can be generalized to many problems, in various fields, ranging from engineering to economics as well as biology.

• ETRI Journal
• /
• v.35 no.3
• /
• pp.439-447
• /
• 2013

To increase device memory yield, many manufacturers use incorporated redundancy to replace faulty cells. In this redundancy technology, the implementation of an effective redundancy analysis (RA) algorithm is essential. Various RA algorithms have been developed to repair faults in memory. However, nearly all of these RA algorithms have low analysis speeds. The more densely compacted the memory is, the more testing and repair time is needed. Even if the analysis speed is very high, the RA algorithm would be useless if it did not have a normalized repair rate of 100%. In addition, when the number of added spares is increased in the memory, then the memory space that must be searched with the RA algorithms can exceed the memory space within the automatic test equipment. A very efficient RA algorithm using simple calculations is proposed in this work so as to minimize both the repair time and memory consumption. In addition, the proposed algorithm generates an optimal solution using a tree-based algorithm in each fault group. Our experiment results show that the proposed RA algorithm is very efficient in terms of speed and repair.