• Journal of Space Technology and Applications
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• v.3 no.4
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• pp.333-341
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• 2023

This study aims to develop technology for testing and verifying the space radiation environment of miniature space components using the facilities of the domestic 100 MeV proton accelerator and the Space Component Test Facility at the Space Testing Center. As advancements in space development progress, high-performance satellites increasingly rely on densely integrated circuits, particularly in core components components like memory. The application of semiconductor components in essential devices such as solar panels, optical sensors, and opto-electronics is also on the rise. To apply these technologies in space, it is imperative to undergo space environment testing, with the most critical aspect being the evaluation and testing of space components in high-energy radiation environments. Therefore, the Space Testing Center at the Korea testing laboratory has developed a radiation testing device for memory components and conducted radiation impact assessment tests using it. The investigation was carried out using 100 MeV protons at a low flux level achievable at the Gyeongju Proton Accelerator. Through these tests, single event upsets observed in memory semiconductor components were confirmed.

• Journal of the Korean Institute of Telematics and Electronics A
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• v.31A no.8
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• pp.111-121
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• 1994

This paper proposes a memory testable code called MTA(Memory TestAble) code which is based on error correcting code technique for testing functional faults in semiconductor memories. The characteristics of this code are analyzed and compared with those of conventional codes. The developed decoding technique for this code can reduce the decoder circuits up to 70% and obtain two-times faster decoding speed than other codes such as hamming code or Hsiao code. The MTA code is eccectively applicable to parallel testing of semiconductor memories because it has the same information length and parity length. It can detect from single error functional faults to triple error in semiconductor memories.

• Smart Structures and Systems
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• v.30 no.3
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• pp.255-261
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• 2022

When no extensometer is available in a generic tensile-compression test carried out by a universal testing machine (for instance the model BIONIX from Material Testing Systems (MTS)), the test results only provide the relative displacement between the machine grips. The test does not provide any information on the local behaviour of the material. This contribution presents the potential of an application of Digital Image Correlation (DIC) toward the reconstruction of the behaviour along the specimen. In particular, the authors test a Ni-Ti shape memory alloys (SMA) specimen with emphasis on the coupling of the two measurement techniques.

• Journal of the Institute of Electronics Engineers of Korea SD
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• v.45 no.2
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• pp.69-81
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• 2008

The density of Memory has been increased by great challenge for memory technology, so elements of memory become smaller than before and the sensitivity to faults increases. As a result of these changes, memory testing becomes more complex. The number of storage elements is increased per chip, and the cost of test becomes more remarkable as the cost per transistor drops. Proposed design doesn't need to control from outside environment, because it integrates into memory. The proposed scheme supports the various memory testing algorithms. Consequently, the proposed one is more efficient in terms of test cost and test data to be applied. Moreover, we proposed a reallocation algorithm for faulty memory parts. It has an efficient reallocation scheme with row and column redundant memory. Previous reallocation information is obtained from faulty memory every each tests. However proposed scheme avoids to this problem. because onetime test result from reallocation information can save to flash memory. In this paper, a reallocation scheme has been increased efficiency because of using flash memory.

• Journal of the Institute of Electronics Engineers of Korea SD
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• v.45 no.9
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• pp.33-40
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• 2008

As the speed of memory is improved vey fast the advanced test equipments are needed to test the ultra-high speed memory devices efficiently. It is necessary to develop the Algorithmic Pattern Generator (ALPG) that tests fast memory devices effectively using the instructions that testers want to use. In this paper, we propose a new parallel ALPG for the ultra-high speed memory testing. The proposed ALPG can generate patterns for fast memory devices at high speed using manual instructions by the Instruction Analyzer.

• Journal of KIISE:Computer Systems and Theory
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• v.35 no.6
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• pp.284-292
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• 2008

The density of Memory has been increased by great challenge for memory technology; therefore, elements of memory become more smaller than before and the sensitivity to faults increases. As a result of these changes, memory testing becomes more complex. In addition, as the number of storage elements per chip increases, the test cost becomes more remarkable as the cost per transistor drops. Recent development in system-on-chip(SoC) technology makes it possible to incorporate large embedded memories into a chip. However, it also complicates the test process, since usually the embedded memories cannot be controlled from the external environment. We present a ARM processor-programmable built-in self-test(BIST) scheme suitable for embedded memory testing in the SoC environment. The proposed BIST circuit can be programmed vis an on-chip microprocessor.

• The Korean Journal of Applied Statistics
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• v.26 no.1
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• pp.163-185
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• 2013

In this paper, we investigate the need to employ long-memory volatility models in terms of Value-at-Risk(VaR) estimation. We estimate the VaR of the KOSPI returns using long-memory volatility models such as FIGARCH and FIEGARCH; in addition, via back-testing we compare the performance of the obtained VaR with short memory processes such as GARCH and EGARCH. Back-testing says that there exists a long-memory property in the volatility process of KOSPI returns and that it is essential to employ long-memory volatility models for the right estimation of VaR.

• Journal of the Institute of Electronics Engineers of Korea SD
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• v.38 no.10
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• pp.746-753
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• 2001

GenBIST implemented in this paper is an automatic CAD tool, which can automatically generate circuitry in VerilogHDL code based on user defined information for the memory testing. While most commercial and conventional CAD tools adopt a method in which they make memory-testing algorithms as a library to generate circuitry, our tool can generate circuitry according to the user-defined algorithm, which makes application of various algorithms easier. In addition, memory BIST circuitry can be shared with other memories by supporting embedded memories in our tool. Also, extra pins for the memory testing are not requited when boundary scan technique is combined.

• Journal of the Institute of Electronics Engineers of Korea SD
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• v.40 no.1
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• pp.72-79
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• 2003

Due to the improvements in circuit design technique and manufacturing technique, complexity of a circuit is growing along with the demand for memories with large capacities. Likewise, as a memory capacity gets larger, testing gets harder and testing cost increases, and testing process in chip development gets larger as well. Therefore, a research on an effective test algorithm to improve the chip yield rate in a short time period is becoming an important task. This paper proposes an effective, March C-algorithm based, test algorithm that can also be applied to a dual-port memory since it considers all the fault types, which can be occurred in a single-port as well as in a dual-port memory, without increasing the test length.

• The Transactions of The Korean Institute of Electrical Engineers
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• v.68 no.2
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• pp.364-369
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• 2019

Generally, since memory chips should be tested all, considering its volume, the reduction in test time for detecting faults plays an important role in reducing the overall production cost. The parallel testing of chips in one ATE is a competitive solution to solve it. In this paper, NOC is proposed as test interface architecture between DUTs and ATE. Because NOC can be extended freely, there is no limit on the number of DUTs tested at the same time. Thus, more memory can be tested with the same bandwidth of ATE. Furthermore, the proposed NOC-based parallel test method can increase the efficiency of channel usage by packet type data transmission.