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An Effective Parallel ALPG for High Speed Memory Testing Using Instruction Analyzer  

Yoon, Hyun-Jun (Department of Electrical and Electronic Engineering, Yonsei University)
Yang, Myung-Hoon (Department of Electrical and Electronic Engineering, Yonsei University)
Kim, Yong-Joon (Department of Electrical and Electronic Engineering, Yonsei University)
Park, Young-Kyu (Department of Electrical and Electronic Engineering, Yonsei University)
Park, Jae-Seok (Department of Electrical and Electronic Engineering, Yonsei University)
Kang, Sung-Ho (Department of Electrical and Electronic Engineering, Yonsei University)
Publication Information
Journal of the Institute of Electronics Engineers of Korea SD / v.45, no.9, 2008 , pp. 33-40 More about this Journal
Abstract
As the speed of memory is improved vey fast the advanced test equipments are needed to test the ultra-high speed memory devices efficiently. It is necessary to develop the Algorithmic Pattern Generator (ALPG) that tests fast memory devices effectively using the instructions that testers want to use. In this paper, we propose a new parallel ALPG for the ultra-high speed memory testing. The proposed ALPG can generate patterns for fast memory devices at high speed using manual instructions by the Instruction Analyzer.
Keywords
ALPG; Algorithmic Pattern Generator; Memory test; Instruction Analyzer;
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