• 한국마이크로전자및패키징학회:학술대회논문집
• /
• 한국마이크로전자및패키징학회 2005년도 ISMP
• /
• pp.111-129
• /
• 2005

Pop provides OEMs and EMS with a platform to cost effectively expand options for logic + memory 3D integration - Expands device options by simplifying business logistics of stacking - Integration controlled at the system level to best match stacked combinations with system requirements - Eliminates margin stacking and expands technology reuse - Helps manage the huge cost impacts associated with increasing demand for multi media processing and memory. PoP is well timed to enable and leverage: - Mass customization of systems for different use (form, fit and function) requirements o Bband and apps processor + memory stack platforms - Logic transition to flip chip enables PoP size reduction o Area and height reduction. Industry standardization is progressing. Amkor provides full turn-key support for base package, memory package and full system integration.

• 한국재료학회지
• /
• 제17권7호
• /
• pp.347-351
• /
• 2007

Vertical interconnect technology called 3D stacking has been a major focus of the next generation of IC industries. 3D stacked devices in the vertical dimension give several important advantages over conventional two-dimensional scaling. The most eminent advantage is its performance improvement. Vertical device stacking enhances a performance such as inter-die bandwidth improvements, RC delay mitigation and geometrical routing and placement advantages. At present memory stacking options are of great interest to many industries and research institutes. However, these options are more focused on a form factor reduction rather than the high performance improvements. In order to improve a stacked device performance significantly vertical interconnect technology with wafer level stacking needs to be much more progressed with reduction in inter-wafer pitch and increases in the number of stacked layers. Even though 3D wafer level stacking technology offers many opportunities both in the short term and long term, the full performance benefits of 3D wafer level stacking require technological developments beyond simply the wafer stacking technology itself.

• 마이크로전자및패키징학회지
• /
• 제19권1호
• /
• pp.25-32
• /
• 2012

Package for artificial satellite is to produce mass production for high package with reliability certification as well as develop SDRAM (synchronous dynamic RAM) module which has such as miniaturization, mass storage, and high reliability in space environment. It requires sophisticated technology with chip stacking or package stacking in order to increase up to 4Gbits or more for mass storage with space technology. To make it better, we should secure suitable processes by doing design, manufacture, and debugging. Pin type PCB substrate was then applied to QFP-Pin type 3D memory package fabrication. These results show that the 3D memory package for artificial satellite scheme is a promising candidate for the realization of our own domestic technologies.

• 한국마이크로전자및패키징학회:학술대회논문집
• /
• 한국마이크로전자및패키징학회 2005년도 ISMP
• /
• pp.89-110
• /
• 2005

A new 3D integration technology using wafer-to-wafer and chip-to-wafer stacking method was described. It was demonstrated that 3D microprocessor, 3D shared memory, 3D image processing chip and 3D artificial retina chip fabricated using 3D integration technology were successfully operated. The possibility of applying 3D image processing chip and 3D artificial retina chip to Robot's eye was investigated. The possibility of implanting 3D artificial retina chip into human eye was investigated.

• ETRI Journal
• /
• 제33권6호
• /
• pp.904-913
• /
• 2011

Three-dimensional (3D) memories using through-silicon vias (TSVs) as vertical buses across memory layers will likely be the first commercial application of 3D integrated circuit technology. The memory dies to stack together in a 3D memory are selected by a die-selection method. The conventional die-selection methods do not result in a high-enough yields of 3D memories because 3D memories are typically composed of known-good-dies (KGDs), which are repaired using self-contained redundancies. In 3D memory, redundancy sharing between neighboring vertical memory dies using TSVs is an effective strategy for yield enhancement. With the redundancy sharing strategy, a known-bad-die (KBD) possibly becomes a KGD after bonding. In this paper, we propose a novel die-selection method using KBDs as well as KGDs for yield enhancement in 3D memory. The proposed die-selection method uses three search-space conditions, which can reduce the search space for selecting memory dies to manufacture 3D memories. Simulation results show that the proposed die-selection method can significantly improve the yield of 3D memories in various fault distributions.

• 반도체디스플레이기술학회지
• /
• 제14권2호
• /
• pp.41-45
• /
• 2015

From 20nm technology node, the finFET has become standard device for ULSI's. However, the finFET process made stacking gate non-volatile memory obsolete. Some reported capacitor-less DRAM structure by utilizing the FBE. We present possible non-volatile memory device structure similar to the dual gate MOSFET. One of the gates is left floating. Since body of the finFET is only 40nm thick, control gate bias can make electron tunneling through the floating gate oxide which sits across the body. For programming, gate is biased to accumulation mode with few volts. Simulation results show that the programming electron current flows at the interface between floating gate oxide and the body. It also shows that the magnitude of the programming current can be easily controlled by the drain voltage. Injected electrons at the floating gate act similar to the body bias which changes the threshold voltage of the device.

• 정보처리학회논문지:컴퓨터 및 통신 시스템
• /
• 제4권2호
• /
• pp.41-46
• /
• 2015

컴퓨터 사용 환경이 모바일 시장 및 소형 전자기기 시장 등으로 다양해짐에 따라 저전력 고성능 시스템에 대한 요구도 커지고 있다. 3차원 die-stacking 기술은 한정된 공간에서 DRAM의 집적도과 접근 속도를 높여 차세대 공정방식으로 많은 연구가 되고 있다. 이 논문에서는 3차원 구조의 DRAM 로직층에 재구성형 가속기를 구현하여 저전력 고성능 시스템을 구성하는 방법을 제안한다. 또한 재구성형 가속기의 지역 메모리로 캐시를 적용하고 활용하는 방법에 대해서 논의한다. DRAM의 로직층에 재구성형 가속기를 구현할 경우 위치적인 특성으로 데이터 전송 및 관리에 필요한 비용이 줄어들어 성능을 크게 향상시킬 수 있다. 제안된 시스템에서는 최대 24.8의 스피드업을 기록하였다.

• 한국정보통신학회논문지
• /
• 제15권3호
• /
• pp.521-527
• /
• 2011

군용 Single Board Computer(이하 SBC)에 주로 사용되는 중앙 처리 장치(Central Processing Unit)는 주로 Power PC의 계열이며 Freescale 사의 G4 계열인 74xx 프로세서가 주로 사용된다. 이러한 CPU인 7447A는 System Controller를 통하여 SBC 내의 주 기억 장치와 고속으로 데이터를 주고받는다. 본 논문에서는 위와 같은 SBC의 구조에서 System Controller와 DDR 메모리 소자 간 I/F를 구현함에 있어 PCB 적층 구조, 소자들의 Layout, 임피던스매칭과 Rugged 환경에서 적용 되는 동작 가능한 DDR 메모리를 모듈로 설계하여 구현하였다. 또한, 군용환경에 적용하기위한 SBC의 형상은 주로 6U, 3U의 표준 형태로 설계되어져야 한다. 메모리의 단종을 대비하여 메모리를 모듈화하고 System Controller와 모듈간의 최적의 전기적인 I/F매칭과 신호의 cross over를 고려한 Artwork반영, 존재하는 PCB의 제한조건을 고려해서 시뮬레이션과 설계 및 구현하는 방안을 제안한다.

• 한국전기전자재료학회:학술대회논문집
• /
• 한국전기전자재료학회 2009년도 하계학술대회 논문집
• /
• pp.415-416
• /
• 2009

The tunnel barrier engineered charge trap flash (TBE-CTF) non-volatile memory using CRESTED tunneling barrier was fabricated by stacking thin $Si_3N_4$ and $SiO_2$ dielectric layers. Moreover, high-k based $HfO_2$ charge trap layer and $Al_2O_3$ blocking layer were used for further improvement of the NVM (non-volatile memory) performances. The programming/erasing speed, endurance and data retention of TBE-CTF memory was evaluated.

• 한국전자파학회지:전자파기술
• /
• 제24권2호
• /
• pp.51-57
• /
• 2013

The current expanding mobile markets incessantly demands small form factor, low power consumption and high aggregate throughput for silicon-level integration such as memory to logic system. One of emerging solution for meeting this high market demand is 3D through silicon stacking (TSS) technology. Main challenges to bring 3D TSS technology to the volume production level are establishing a cost effective supply chain and building a reliable manufacturing processes. In addition, this technology inherently help increase number of IOs and shorten interconnect length. With those benefits, however, potential signal and power integrity risks are also elevated; increase in PDN inductance, channel loss on substrate, crosstalk and parasitic capacitance. This paper will report recent progress of wide IO memory to high count TSV logic device assembly development work. 28 nm node TSV test vehicles were fabricated by the foundry and assembled. Successful integration of memory wide IO chip with less than a millimeter package thickness form factor was achieved. For this successful integration, we discussed potential signal and power integrity challenges. This report demonstrated functional wide IO memory to 28 nm logic device assembly using 3D package architecture with such a thin form factor.