• Korean Journal of Materials Research
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• v.19 no.9
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• pp.462-467
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• 2009

The Charge Trap Flash (CTF) memory device is a replacement candidate for the NAND Flash device. In this study, Pt/$Al_2O_3/La_2O_3/SiO_2$/Si multilayer structures with lanthanum oxide charge trap layers were fabricated for nonvolatile memory device applications. Aluminum oxide films were used as blocking oxides for low power consumption in program/erase operations and reduced charge transports through blocking oxide layers. The thicknesses of $SiO_2$ were from 30 $\AA$ to 50 $\AA$. From the C-V measurement, the largest memory window of 1.3V was obtained in the 40 $\AA$ tunnel oxide specimen, and the 50 $\AA$ tunnel oxide specimen showed the smallest memory window. In the cycling test for reliability, the 30 $\AA$ tunnel oxide sample showed an abrupt memory window reduction due to a high electric field of 9$\sim$10MV/cm through the tunnel oxide while the other samples showed less than a 10% loss of memory window for $10^4$ cycles of program/erase operation. The I-V measurement data of the capacitor structures indicated leakage current values in the order of $10^{-4}A/cm^2$ at 1V. These values are small enough to be used in nonvolatile memory devices, and the sample with tunnel oxide formed at $850^{\circ}C$ showed superior memory characteristics compared to the sample with $750^{\circ}C$ tunnel oxide due to higher concentration of trap sites at the interface region originating from the rough interface.

• Journal of the Korea Academia-Industrial cooperation Society
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• v.4 no.3
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• pp.177-182
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• 2003

In the case of the flash memory, various kinds of transistors and the wide range of operation voltage are necessary to achieve the read/write operations. Therefore, the characteristics of transistors are measured in the silicon for the circuit design, and the test vehicle run must be processed. In this study, an efficient design flow is suggested using TCAD tools. The test vehicle is replaced with well-calibrated TCAD simulation. First, the calibration methodology is introduced and tested for flash memory device. The calibration errors are less than 5% of a full chip operation, which is accepted by the designers. The results of the calibration were used to predict I-V curves and model parameter of the various transistors for the design of flash device.

• JSTS:Journal of Semiconductor Technology and Science
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• v.15 no.6
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• pp.658-663
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• 2015

In the previous work, we have proposed an integrate-and-fire neuron circuit and synaptic device based on the floating body MOSFET [1-3]. Integrate-and-Fire(I&F) neuron circuit emulates the biological neuron characteristics such as integration, threshold triggering, output generation, refractory period using floating body MOSFET. The synaptic device has short-term and long-term memory in a single silicon device. In this paper, we connect the neuron circuit and the synaptic device using current mirror circuit for summation of post synaptic pulses. We emulate spike-timing-dependent-plasticity (STDP) characteristics of the synapse using feedback voltage without controller or clock. Using memory device in the logic circuit, we can emulate biological synapse and neuron with a small number of devices.

• Proceedings of the Korean Vacuum Society Conference
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• 2014.02a
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• pp.289.1-289.1
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• 2014

In this study, we made a organic thin film device in MIS(Metal-Insulator-Semiconductor) structure by using PVP (Poly vinyl phenol) as a insulating layer, and CdSe/ZnS nano particles which have a core/shell structure inside. We dissolved PVP and PMF in PGMEA, organic solvent, then formed a thin film through a spin coating. After that, it was cross-linked by annealing for 1 hour in a vacuum oven at $185^{\circ}C$. We operated FTIR measurement to check this, and discovered the amount of absorption reduced in the wave-length region near 3400 cm-1, so could observe decrease of -OH. Boonton7200 was used to measure a C-V relationship to confirm a properties of the nano particles, and as a result, the width of the memory window increased when device including nano particles. Additionally, we used HP4145B in order to make sure the electrical characteristics of the organic thin film device and analyzed a conduction mechanism of the device by measuring I-V relationship. When the voltage was low, FNT occurred chiefly, but as the voltage increased, Schottky Emission occurred mainly. We synthesized CdSe/ZnS and to confirm this, took a picture of Si substrate including nano particles with SEM. Spherical quantum dots were properly made. Due to this study, we realized there is high possibility of application of next generation memory device using organic thin film device and nano particles, and we expect more researches about this issue would be done.

• Proceedings of the Korean Vacuum Society Conference
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• 2014.02a
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• pp.368.1-368.1
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• 2014

We proposed amorphous GeSe-based ReRAM device of metal-insulator-metal (M-I-M) structure. The operation characteristics of memory device occured unipolar switching characteristics. By introducing the concepts of valance-alternation-pairs (VAPs) and chalcogen vacancies, the unipolar resistive switching operation had been explained. In addition, the current transport behavior were analyzed with space charge effect of VAPs, Schottky emission in metal/GeSe interface and P-F emission by GeSe bulk trap in mind. The GeSe ReRAM device of M-I-M structure indicated the stable memory switching characteristics. Furthermore, excellent stability, endurance and retention characteristics were also verified.

• Journal of the Institute of Electronics and Information Engineers
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• v.51 no.8
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• pp.172-177
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• 2014

We present on a threshold switching device based on AsGeTeSi material which is significantly improved by two $N_2$ processes: reactive $N_2$ during deposition, and $N_2$ plasma hardening. The introduction of N2 in the two-step processing enables a stackable and thermally stable device structure, is allowing integration of switch and memory devices for application in nano scale array circuits. Despite of its good threshold switching characteristics, AsTeGeSi-based switches have had key issues with reliability at a high temperature to apply resistive memory. This is usually due to a change in a Te concentration. However, our chalconitride switches(AsTeGeSiN) show high temperature stability as well as high current density over $1.1{\times}10^7A/cm^2$ at $30{\times}30(nm^2)$ celll. A cycling performance of the switch was over $10^8$ times. In addition, we demonstrated a memory cell consisted of 1 switch-1 resistor (1S-1R) stack structure using a TaOx resistance memory with the AsTeGeSiN select device.

• Journal of KIISE:Computer Systems and Theory
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• v.30 no.5_6
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• pp.232-238
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• 2003

Traditional operating systems use a virtual memory to provide users with a bigger memory than a physical memory. The virtual memory augments the insufficient physical memory by the swap device. Since disks are usually used as the swap device, the cost of a page fault is relatively high compared to the access cost of the physical memory. Recently, numerous papers have investigated the Network RAM in order to exploit the idle memory in the network instead of disks. Since today's distributed systems are interconnected with high-performance networks, the network latency is far smaller than the disk access latency In this paper we design and implement the Network RAM using block device driver on Linux. This is the first implementation of the Network RAM on Linux. We propose the new reliability method to recover the page when the other workstation's memory is damaged. The system using the Network RAM as the swap device reduces the execution time by 40.3% than the system using the disk as the swap device. The performance results suggest that the new reliability method that use the processor more efficiently has the similar execution time with others, but uses smaller server memory and generates less message traffic than others.

• Journal of the Korean Vacuum Society
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• v.21 no.6
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• pp.354-361
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• 2012

The organic memory device was made by the plasma polymerization method which was not the dry process but the wet process. The memory device consist of the styrene and MMA monomer as the insulating layer, MMA monomer as the tunneling layer and Au thin film as the memory layer which was fabricated by thermal evaporation method. The I-V characteristics of fabricated memory device got the hysteresis voltage of 27 V at 40/-40 V double sweep measuring conditions. At this time, the optimized structure was 7 nm of Au thin film as floating gate, 400 nm of styrene thin film as insulating layer and 30 nm of MMA thin film as tunneling layer. Therefore we got the charge trapping characteristics by the hysteresis voltage. From the paper, styrene indicated a good charge trapping characteristics better than MMA. In the future, we expect to make devices by using styrene thin film rather than Au thin film.

• Journal of Internet of Things and Convergence
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• v.7 no.4
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• pp.9-14
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• 2021

In computing systems that require high reliability, the method of predicting the lifetime of a storage device is one of the important factors for system management because it can maximize usability as well as data protection. The life of a solid state drive (SSD) that has recently been used as a storage device in several storage systems is linked to the life of the NAND flash memory that constitutes it. Therefore, in a storage system configured using an SSD, a method of accurately and efficiently predicting the lifespan of a NAND flash memory is required. In this paper, a method for optimizing the lifetime prediction of a flash memory-based storage device using the frequency of NAND flash memory failure is proposed. For this, we design a cost matrix to collect the frequency of defects that occur when processing data in units of Drive Writes Per Day (DWPD). In addition, a method of predicting the remaining cost to the slope where the life-long finish occurs using the Gradient Descent method is proposed. Finally, we proved the excellence of the proposed idea when any defect occurs with simulation.

• JSTS:Journal of Semiconductor Technology and Science
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• v.8 no.1
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• pp.51-65
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• 2008

The article presents the recent research development in polymer ferroelectric non-volatile memory. A brief overview is given of the history of ferroelectric memory and device architectures based on inorganic ferroelectric materials. Particular emphasis is made on device elements such as metal/ferroelectric/metal type capacitor, metal-ferroelectric-insulator-semiconductor (MFIS) and ferroelectric field effect transistor (FeFET) with ferroelectric poly(vinylidene fluoride) (PVDF) and its copolymers with trifluoroethylene (TrFE). In addition, various material and process issues for realization of polymer ferroelectric non-volatile memory are discussed, including the control of crystal polymorphs, film thickness, crystallization and crystal orientation and the unconventional patterning techniques.