• The Transactions of The Korean Institute of Electrical Engineers
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• v.60 no.5
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• pp.965-970
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• 2011

This paper deals with the PM performance evaluations in a pole changing memory motor (PCMM) using a coupled transient finite element method (FEM) and Preisach modeling, which is presented to analyze the magnetic characteristics of permanent magnets. The focus of this paper is the characteristics evaluation relative to magnetizing direction and the pole number of machine on re-demagnetization condition in a pole changing memory motor.

• Journal of the Korean Institute of Telematics and Electronics D
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• v.35D no.7
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• pp.32-39
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• 1998

This paper presents the experimental results on the 3-electrode DC-PDP which has a common electrode to improve the PDP life cycle. The measured DC characteristic proves the effectiveness of common electrode absorbing about half of discharge currents. The waveforms for pulse memory operation of3-electrode PDP without crosstalk could also be determined from the I-V characteristics. The pulse memory drives of 8*8 cell array show the frequency response fo memory margin and the luminance efficiency of 3-electrode PDP are quite different from genrally known characteristics of 2-electrode DC-PDP.

• Proceedings of the Korea Information Processing Society Conference
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• 2020.11a
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• pp.20-23
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• 2020

This research is to design an effective prefetching method required for DRAM-PCM hybrid main memory systems especially used for big data applications and massive-scale computing environment. Conventional prefetchers perform well with regular memory access patterns. However, workloads such as graph processing show extremely irregular memory access characteristics and thus could not be prefetched accurately. Therefore, this research proposes an efficient dynamical prefetching algorithm based on the regression method. We have designed an intelligent prefetch engine that can identify the characteristics of the memory access sequences. It can perform regular, linear regression or polynomial regression predictive analysis based on the memory access sequences' characteristics, and dynamically determine the number of pages required for prefetching. Besides, we also present a DRAM-PCM hybrid memory structure, which can reduce the energy cost and solve the conventional DRAM memory system's thermal problem. Experiment result shows that the performance has increased by 40%, compared with the conventional DRAM memory structure.

• Proceedings of the Korean Society of Precision Engineering Conference
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• 2001.04a
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• pp.683-686
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• 2001

The thermomechanical characteristics of NITINOL shape memory alloy were evaluated using DSC with small samples and DMA with three-point bending specimens. The shape memory alloy of 54.4Ni/45.5Ti wt.% was used so that the austenite finish temperature was in the range of $50~100^{\circ}C$. Two types of sample were tested in the experiments corresponding to as-received and annealed conditions. Simple beam bending theory was used to calculate the dynamic moduli of the shape memory alloy. According to the results, a large discrepancy in transformation temperatures was found between DSC and DMA techniques. Annealing treatment was found to suppress the R-phase transformation during cooling and the secondary plateau in the austenite transformation. Such a heat treatment was also significantly influenced to raise the transformation temperatures and the moduli of the shape memory alloy.

• Proceedings of the Korean Institute of Electrical and Electronic Material Engineers Conference
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• 2002.07a
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• pp.26-31
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• 2002

To realize a high integrated Flash memory utilizing SONOS memory devices, the NOR type 1TC(one Transistor Cell) SONOS Flash arrays are fabricated and characterized. This SONOS Flash arrays with common source lines are designed and fabricated by conventional 0.35$\mu\textrm{m}$ CMOS process. The thickness of ONO for memory cell is tunnel oxide of 34${\AA}$, nitride of 73${\AA}$ and blocking oxide of 34${\AA}$. To investigate operating characteristics, CHEI(Channel Hot Electron Injection) method and Bit line erase method are selected as the write operation and the erase method, respectively. The disturbance characteristics according to the write/erase/read cycling are also examined. The degradation characteristics are investigated and then the reliability of SONOS flash memory is guaranteed.

• Journal of the Korean Institute of Electrical and Electronic Material Engineers
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• v.16 no.5
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• pp.372-377
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• 2003

To realize a high integrated flash memory utilizing SONOS memory devices, the NOR type ITC(one Transistor Cell) SONOS flash arrays are fabricated and characterized. This SONOS flash arrays with the common source lines are designed and fabricated by conventional 0.35$\mu\textrm{m}$ CMOS process. The thickness of ONO for memory cells is tunnel oxide of 34${\AA}$, nitride of 73${\AA}$ and blocking oxide of 34${\AA}$ . To investigate operating characteristics, CHEI(Channel Hot Electron Injection) method and bit line method are selected as the program and 4he erase operation, respectively. The disturbance characteristics ,according to the program/erase/read cycling are also examined. The degradation characteristics are investigated and then the reliability of SONOS flash memory is guaranteed.

• IEMEK Journal of Embedded Systems and Applications
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• v.11 no.2
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• pp.117-123
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• 2016

In general, PCM (Phase Change Memory) is unsuitable as a main memory because it has limitations: high read/write latency and low endurance. However, the DRAM&PCM hybrid memory with the same level is one of the effective structures for a next generation main memory because it can utilize an advantage of both DRAM and PCM. Therefore, it needs an effective page management method for exploiting each memory characteristics dynamically and adaptively. So we aim reducing an access time and write count of PCM by using an effective page replacement. According to our simulation, the proposed algorithm for the DRAM&PCM hybrid can reduce the PCM access count by around 60% and the PCM write count by 42% given the same PCM size, compared with Clock-DWF algorithm.

• International journal of advanced smart convergence
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• v.12 no.4
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• pp.164-170
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• 2023

With the recent advances in AI (artificial intelligence) and HPC (high-performance computing) technologies, deep learning is proliferated in various domains of the 4th industrial revolution. As the workload volume of deep learning increasingly grows, analyzing the memory reference characteristics becomes important. In this article, we analyze the memory reference traces of deep learning workloads in comparison with traditional workloads specially focusing on read and write operations. Based on our analysis, we observe some unique characteristics of deep learning memory references that are quite different from traditional workloads. First, when comparing instruction and data references, instruction reference accounts for a little portion in deep learning workloads. Second, when comparing read and write, write reference accounts for a majority of memory references, which is also different from traditional workloads. Third, although write references are dominant, it exhibits low reference skewness compared to traditional workloads. Specifically, the skew factor of write references is small compared to traditional workloads. We expect that the analysis performed in this article will be helpful in efficiently designing memory management systems for deep learning workloads.

• Proceedings of the Korean Vacuum Society Conference
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• 2010.02a
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• pp.241-241
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• 2010

New non-volatile memory with high density and high work-function metal nano-dots, MND (Metal Nano-Dot) memory, was proposed and fundamental characteristics of MND capacitor were evaluated. In this work, nano-dot layer of FePt with high density and high work-function (~5.2eV) was fabricated as a charge storage site in non-volatile memory, and its electrical characteristics were evaluated for the possibility of non-volatile memory in view of cell operation by Fowler-Nordheim (FN)-tunneling. Here, nano-dot FePt layer was controlled as a uniform single layer with dot size of under ~ 2nm and dot density of ${\sim}\;1.2{\times}10^{13}/cm^2$. Electrical measurements of MOS structure with FePt nano-dot layer shows threshold voltage window of ~ 6V using FN programming and erasing, which is satisfied with operation of the non-volatile memory. Furthermore, this structure provides better data retention characteristics compared to other metal dot materials with the similar dot density in our experiments. From these results, it is expected that this non-volatile memory using FePt nano-dot layer with high dot density and high work-function can be one of candidate structures for the future non-volatile memory.

• Journal of the Korean Institute of Electrical and Electronic Material Engineers
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• v.11 no.1
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• pp.57-61
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• 1998

In this study, PLZT stock solutions were prepared by Sol-Gel processing after the compositions were selected in the memory region of PLZT bulk phase diagram. PLZT solutions were deposited on the ITO glass substrate by spin-coating method. The thin films were annealed by rapid thermal processing. The electric characteristics, hysteresis loop, C-V characteristics of thin films in the memory region were measured in order to investigate the electrical characteristics of PLZT thin films. In selected compositions the decrease in Zr/Ti ratio led to an increase in dielectric constant and the decrease in remanent polarization and coercieve field which brought about slim hysteresis loop.