• JSTS:Journal of Semiconductor Technology and Science
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• 제11권3호
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• pp.162-168
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• 2011

In this paper, we propose a new Verilog-A current-voltage model for multi-level-cell PCRAMs. This model can describe the PCRAM operation not only in full SET and RESET states but also in the partial resistance states. And, 3 PCRAM operating regions of SET-RESET, Negative Differential Resistance, and strong-ON are unified into one equation in this model thereby any discontinuity that may introduce a convergence problem cannot be found in the new PCRAM model. The percentage error between the measured data and this model is as small as 7.4% on average compared to 60.1% of the previous piecewise model. The parameter extraction which is embedded in the Verilog-A code can be done automatically.

• 제어로봇시스템학회:학술대회논문집
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• 제어로봇시스템학회 1997년도 한국자동제어학술회의논문집; 한국전력공사 서울연수원; 17-18 Oct. 1997
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• pp.716-719
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• 1997

An integrated program of driving simulator has been developed for excavators using the Motif, OpenGL, and C compiler. The developed program not only offers a GUI but also covers graphic algorithms, therefore, the user can easily run the driving simulator whose components include a simplified visual graphics system. Several graphics technique are combined and applied to the simulator program in order to increase the speed of graphical representation, which access computer memories, mix 2D models with 3D ones, and use the basic position detection method. A text format environment file has been utilized for organizing more flexible driving circumstances.

• 대한전자공학회:학술대회논문집
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• 대한전자공학회 2002년도 ITC-CSCC -1
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• pp.694-697
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• 2002

Sampling rate conversion widely used in subband coding, A/D and D/A transitions etc. is an important techniques. Nyquist filters and the filter banks have been used far the sampling converter. However, they need many memories and, whenever the sampling rate is changed it is necessary to redesign filters. Then we propose design method of the new interpolation kernel. Design method of the new interpolation kernel is approximated each piecewise of lowpass filter by n th polynomials. The proposed kernel is not redesigned, whenever the sampling rate is changed. The proposed kernel is a continuous function, the sampling rate of the rational number can be converted.

• 대한전자공학회:학술대회논문집
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• 대한전자공학회 2004년도 하계종합학술대회 논문집(2)
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• pp.469-472
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• 2004

In this paper a current mode sense amplifier suitable for 30nm SONOS flash memories read operation is presented. The proposed sense amplifier employs cross coupled latch type circuit and current mirror to amplify signal from selected memory cell. This sense amplifier provides fast response in low voltage and low current dissipation. Simulation results show the sensing delay time and current dissipation for power supply voltages Vdd to expose limitations of the sense amplifier in various operating conditions.

• JSTS:Journal of Semiconductor Technology and Science
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• 제9권4호
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• pp.187-191
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• 2009

This paper proposes a high-performance architecture of the H.264 intra prediction circuit. The proposed architecture uses the 4-input and 2-input common computation units and common registers for fast and efficient prediction operations. It avoids excessive power consumption by the efficient control of the external and internal memories. The implemented circuit based on the proposed architecture can process more than 60 HD ($1,920{\times}1,088$) image frames per second at the maximum operating frequency of 101 MHz by using 130 nm standard cell library.

• JSTS:Journal of Semiconductor Technology and Science
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• 제12권4호
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• pp.388-396
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• 2012

In this paper, a $320{\times}240$ pixel, 80 frame/s CMOS image sensor with a low power dual correlated double sampling (CDS) scheme is presented. A novel 8-bit hold-and-go counter in each column is proposed to obtain 10-bit resolution. Furthermore, dual CDS and a configurable counter scheme are also discussed to realize efficient power reduction. With these techniques, the digital counter consumes at least 43% and at most 61% less power compared with the column-counters type, and the frame rate is approximately 40% faster than the double memory type due to a partial pipeline structure without additional memories. The prototype sensor was fabricated in a Samsung $0.13{\mu}m$ 1P4M CMOS process and used a 4T APS with a pixel pitch of $2.25{\mu}m$. The measured column fixed pattern noise (FPN) is 0.10 LSB.

• 한국컴퓨터정보학회논문지
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• 제22권9호
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• pp.1-8
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• 2017

In this paper, we propose a file system for flash memory which remedies shortcomings of existing flash memory file systems. Besides supporting large block size, the proposed file system reduces time in initializing file system significantly by adopting logical address comprised of erase block number and bitmap for pages in the block to find a page. The file system is suitable for embedded systems with limited main memory since it has small in-memory data structures. It also provides efficient management of obsolete blocks and free blocks, which contribute to the reduction of file update time. Finally the proposed file system can easily configure the maximum file size and file system size limits, which results in portability to emerging larger flash memories. By conducting performance evaluation studies, we show that the proposed file system can contribute to the performance improvement of embedded systems.

• 대한기계학회논문집
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• 제18권3호
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• pp.624-634
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• 1994

A numerical method which combines equal-order velocity-pressure formulation originated from SIMPLE algorithm and streamline upwinding method has been developed. To verify the proposed numerical method, we considered the lid-driven cavity flow and backward facing step flow. The trend of convergence history is stable up to the error criterion beyond which the maximum value of error is oscillatory due4 to the round-off error. In the present study, all results were obtained with the single precision calculation up to the given error criterion and it was found to be sufficient for our purpose. The present results were then compared with existing experimental results using laser doppler velocimetry and numerical results using finite difference method and mixed interpolation finite element method. It has been shown that the present method gives accurate results with less memories and execution time than the coventional finite element method.

• Journal of Information Technology Applications and Management
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• 제12권4호
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• pp.59-70
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• 2005

Flash memories are one of best media to support portable computer's storages in mobile computing environment. The features of non-volatility, low power consumption, and fast access time for read operations are sufficient grounds to support flash memory as major database storage components of portable computers. However, we need to improve traditional transaction management scheme due to the relatively slow characteristics of flash operation as compared to RAM memory. in order to achieve this goal, we devise a new scheme called Flash Two Phase Locking (F2PL) scheme for efficient transaction processing. F2Pl improves transaction performance by allowing multi version reads and efficiently handling slow flash write/erase operation in lock management process. We also propose a simulation model to show the performance of F2PL. Based on the results of the performance evaluation, we conclude that F2PL scheme outperforms the traditional scheme.

• 대한전기학회:학술대회논문집
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• 대한전기학회 2004년도 학술대회 논문집 정보 및 제어부문
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• pp.598-601
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• 2004

In this paper, we suggest method that change odors to digital data. For this, we selected emotional adjective of odors as olfactory receptor This emotional adjective(expressional receptor) is about 40. Each odors are expressed by adjective equivalent to oneself. Expressed odors as emotional receptor is encoded as proposed method for transmission, and after transmission, It should be decoded for expression again. The applied decoding method is fuzzy c-means clustering algorithm(FCMA). But, because odor data is expressed to 40 dimensions, FCMA uses a lot of computing times and memories. To solve this problem, after we reduce dimension through principal component analysis(PCA), we use FCMA algorithm.