• The Transactions of the Korean Institute of Electrical Engineers D
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• v.55 no.5
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• pp.229-235
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• 2006

High speed PC-based DIO(Digital I/O) system that consists of a master device and slave I/O devices is developed. The PCI interfaced master device controls all of serial communications, reducing the load on the CPU to a minimum. The slave device is connected from the master device and another slave device is connected to the slave device, it can repeated to maximum 64 slave devices. The slave device has 3 types I/O mode, such as 16 bits input-only, 16 bits output-only, and 8bits input-output. The master device has 2 rings which can take 64 slaves each. Therefore, total I/O points covered by the master is 2048 points. The slave features 3 types of input/output function interchangeability by DIP switch settings. Library, application, and device driver software for the DIO system that have a secure and a convenient functionality are developed.

• ETRI Journal
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• v.34 no.4
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• pp.553-563
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• 2012

Serial peripheral interface (SPI) has been identified as a bottleneck in many wireless sensing systems today. SPI is used almost universally as the physical connection between the microcontroller unit (MCU) and radios, storage devices, and many types of sensors. Virtually all wireless sensor nodes today perform up to twice as many bus transactions as necessary to transfer a given piece of data, as an MCU must serve as the bus master in all transactions. To eliminate this bottleneck, we propose the master-handoff protocol. After the MCU initiates reading from the source slave device and writing to the sink slave device, the MCU as a master becomes a slave, and either the source or the sink slave becomes the temporary master. Experiment results show that this master-handoff technique not only cuts the data transfer time in half, but, more importantly, also enables a superlinear energy reduction.

• The Journal of the Korea Contents Association
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• v.13 no.5
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• pp.19-27
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• 2013

This paper implements the standby power control system composed of a master device and slave devices. The standby power is managed by cutting power supply after controlling the relay of a slave device based on the authentication of master device's RFID card. RFID interface and wireless communication module are embedded in a master device, and one master device is linked with many slave devices in wireless. Each slave device executes the operation needed in power control independently. We implements the function of manual power on/off system in a slave device, and the function of user ID enrollment by switch manipulation in a master device. Also this system can communicate bidirectionally in wireless and runs on TinyOS. The result of experiment shows that the user authentication is executed in a master device and this authenticated information is transmitted to a slave device in wireless, and standby power is cutted by controlling the relay of a slave device. Installing this system in a building or an office, we can expect energy saving.

• Journal of IKEEE
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• v.17 no.3
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• pp.267-274
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• 2013

This paper presents a design of LLC resonant converter IC for LED backlight unit based on PFM/PWM dual-mode feedback. Dual output LLC resonant architecture with a single inductor is proposed, where the master output is controlled by the PFM and slave output is controlled by the PWM. To regulate the master output PFM is used as feedback to control the frequency of the power switch. On the other hand, PWM feedback is used to control the pulse width of the power switch and to regulate the slave output. This chip is fabricated in 0.35um 2P3M BC(Bipolar-CMOS-DMOS) Process and the die area is $2.3mm{\times}2.2mm$. Current consumptions is 26mA from 5V supply.

• The KIPS Transactions:PartA
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• v.18A no.1
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• pp.25-32
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• 2011

NoC is actively being studied recently in order to overcome the limitations of shared-bus architecture. We proposed an NoC architecture which employs a buffer that plays a similar role of a proxy server in a computer network to enhance the communication efficiency of NoC architecture. In the proposed NoC architecture, whenever the master has a difficulty in communicating with the slave directly, the master communicates with the proxy server which is able to communicate with the slave on behalf of the master. With the proposed scheme in NoC, we can increase the speed and the bandwidth of communication channel. The experimental results showed that overall communication efficiency was significantly improved by sending the packets to the proxy server rather than holding them in the switch buffer.

• Proceedings of the KIEE Conference
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• 2005.07d
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• pp.3034-3036
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• 2005

High speed PC-based digital I/O system, PCI-bus master and slave. set is developed, which features are distributed structure, input/output function interchangeability by switch settings, and high speed(20Mbps). Library and application software for a DIO system that have a secure and a convenient functionality are developed.

• Proceedings of the KIEE Conference
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• 2005.07d
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• pp.3031-3033
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• 2005

High speed PC-based digital I/O system hardware, PCI-bus master and slave set is developed, which features are distributed structure, input/output function interchangeability by switch setting, high speed 20Mbps to update 1000 points in less than 1 ms, etc.

• The Journal of Korean Institute of Communications and Information Sciences
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• v.27 no.11C
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• pp.1164-1170
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• 2002

In the ACE2000 MPLS system, MPLS Interface Module(MIM) is composed of an ATM Interface Module and a HFMA performing a packet forwarding. In the MIM, the HFMA RSAR receive cells from the Physical layer and reassemble the cells. And the IP Lookup controller perform a packet forwarding after packet classification. Forwarded packet is segmented into cells in the HFMA TSAR and transfer to the ALMA for the transmission to an ATM cell switch. When the MIM make use of an ATM Interface Module, it directly connect the ALMA with a PHY layer using the UTOPIA Level2 interface. Then, an ALMA performs Master Mode. Also, the HFMA TSAR performs the Master Mode in the MIM. Therefore, the UTOPIA-L2 Controller of the Slave Mode require for interfacing between an ALMA and a HFHA TSAR. In this paper, we implement the architecture and cell control mechanism for the UTOPIA-L2 Controller supporting Multi-ports.

• Journal of the Korea Institute of Information and Communication Engineering
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• v.14 no.3
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• pp.684-690
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• 2010

Most of the existing SoCs have shared bus architecture which always has a bottleneck state. The more IPs are in an SOC, the less performance it is of the SOC, Therefore, its performance is effected by the entire communication rather than CPU speed. In this paper, we propose cross-bar switch bus architecture for the reduction of the bottleneck state and the improvement of the performance. The cross-bar switch bus supports up to 8 masters and 16 slaves and parallel communication with architecture of multiple channel bus. Each slave has an arbiter which stores priority information about masters. So, it prevents only one master occupying one slave and supports efficient communication. We compared WISHBONE on-chip shared bus architecture with crossbar switch bus architecture of the SOC platform, which consists of an OpenRISC processor, a VGA/LCD controller, an AC97 controller, a debug interface, a memory interface, and the performance improved by 26.58% than the previous shared bus.

• Proceedings of the IEEK Conference
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• 2002.07a
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• pp.176-179
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• 2002

In recent years, an increasing amount of computer network research has focused on the problem of cluster system in order to achieve higher performance and lower cost. The load unbalance is the major defect that reduces performance of a cluster system that uses parallel program in a form of SPMD (Single Program Multiple Data). Also, the load unbalance is a problem of MPP (Massive Parallel Processors), and distributed system. The cluster system is a loosely-coupled distributed system, therefore, it has higher communication overhead than MPP. Dynamic load balancing can solve the load unbalance problem of cluster system and reduce its communication cost. The cluster systems considered in this paper consist of P heterogeneous nodes connected by a switch-based network. The master node can predict the average execution time of tasks for each slave node based on the information from the corresponding slave node. Then, the master node redistributes remaining tasks to each node considering the predicted execution time and the communication overhead for task migration. The proposed dynamic load balancing uses execution time prediction to optimize the task redistribution. The various performance factors such as node number, task number, and communication cost are considered to improve the performance of cluster system. From the simulation results, we verified the effectiveness of the proposed dynamic load balancing algorithm.