• 한국정보통신설비학회:학술대회논문집
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• 2006.08a
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• pp.179-182
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• 2006

This paper introduce a different-type voltage-controlled oscillator (VCO) for PLL frequency synthesizer, And also the architecture of a high speed low-power-consumption CMOS dual-modulus frequency divider is presented. It provides a new approach to high speed operation and low power consumption. The proposed circuits simulate in 0.35 um CMOS standard technology.

• Proceedings of the IEEK Conference
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• 1998.10a
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• pp.707-710
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• 1998

This paper presents a new voltage down converter(VDC) for low power, high speed DRAM. This VDC Consists of RVG(Reference Voltage Generator) and Driver Circuit. And it is independent of temperature variation, and Supply Voltage. Using weak inversion region, this RVG dissipates low power. Internal Voltage Source of this VDC is stable in spite of high speed operation of memory array. This circuit is designed with a $0.65\mu\textrm{m}$ nwell CMOS technology. In HSPICE simulation results, Temperature dependency of this RVG is $20\muV/^{\circ}C,$ supply voltage dependency is $\pm0.17%,$ $VCC=3.3V\pm0.3V,$ and current dissipation is $5.22\muA.$ Internal voltage source bouncing of this VDC is smaller than conventional VDC.

• JSTS:Journal of Semiconductor Technology and Science
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• v.6 no.3
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• pp.154-161
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• 2006

This paper describes the new types of ngative differential resistance (NDR) IC applications which use a monolithic quantum-effect device technology based on the RTD/HBT heterostructure design. As a digital IC, a low-power/high-speed MOBILE (MOnostable-BIstable transition Logic Element)-based D-flip flop IC operating in a non-return-to-zero (NRZ) mode is proposed and developed. The fabricated NRZ MOBILE D-flip flop shows high speed operation up to 34 Gb/s which is the highest speed to our knowledge as a MOBILE NRZ D-flip flop, implemented by the RTD/HBT technology. As an analog IC, a 14.75 GHz RTD/HBT differential-mode voltage-controlled oscillator (VCO) with extremely low power consumption and good phase noise characteristics is designed and fabricated. The VCO shows the low dc power consumption of 0.62 mW and good F.O.M of -185 dBc/Hz. Moreover, a high-speed CML-type multi-functional logic, which operates different logic function such as inverter, NAND, NOR, AND and OR in a circuit, is proposed and designed. The operation of the proposed CML-type multi-functional logic gate is simulated up to 30 Gb/s. These results indicate the potential of the RTD based ICs for high speed digital/analog applications.

• Journal of the Korea Institute of Military Science and Technology
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• v.21 no.6
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• pp.826-841
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• 2018

The military satellite communication of ROK military, ANASIS is designed for analog data such as voice and streaming data. ANASIS cannot fully support ALL-IP communications due to its long propagation delay. The next generation satellite communication system is being designed to overcome the limitation. Next generation satellite communications system considers both high-speed and low-speed networks to support various operating environment. The low-speed satellite supports both broadband and narrow-band communication. This network works as the infrastructure for of wide-area internetworking over multiple AS's in the terrestrial network. It requires minimum satellite frequency and minimum power and works without PEP and router. In this paper, we propose a network operation structure to enable the inter-operation between high and low-speed satellite networks. In addition, we propose a data link protocol for low speed satellite networks.

• JSTS:Journal of Semiconductor Technology and Science
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• v.10 no.3
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• pp.176- 184
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• 2010

A low-power inductorless 1:4 DEMUX and a 4:1 MUX for a 90 nm CMOS are presented. The DEMUX can be operated at a speed of 25 Gb/s with the power supply voltage of 1.05 V, and the power consumption is 8.9 mW. The area of the DEMUX core is $29\;{\times}\;40\;{\mu}m^2$. The operation speed of the 4:1 MUX is 13 Gb/s at a power supply voltage of 1.2 V, and the power consumption is 4 mW. The area of the MUX core is $30\;{\times}\;18\;{\mu}m^2$. The MUX/DEMUX mainly consists of differential pseudo-NMOS. In these MUX/DEMUX circuits, logic swing is nearly rail-to-rail, and a low $V_{dd}$. The component circuit is more scalable than a CML circuit, which is commonly used in a high-performance MUX/DEMUX. These MUX/DEMUX circuits are compatible with conventional CMOS logic circuit, and it can be directly connected to CMOS logic gates without logic level conversion. Furthermore, the circuits are useful for core-to-core interconnection in the system LSI or chip-to-chip communication within a multi-chip module, because of its low power, small footprint, and reasonable operation speed.

• JSTS:Journal of Semiconductor Technology and Science
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• v.3 no.2
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• pp.102-106
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• 2003

This paper describes novel low-power high-speed flip-flop called dual edge-triggered NAND keeper flip-flop (DETNKFF). The flip-flop achieves substantial power reduction by incorporating dual edge-triggered operation and by eliminating redundant transitions. It also minimizes the data-to-output latency by reducing the height of transistor stack on the critical path. Moreover, DETNKFF allows negative setup time to provide useful attribute of soft clock edge by incorporating the pulse-triggered operation. The proposed flip-flop was designed using a $0.35{\;}\mutextrm{m}$ CMOS technology. The simulation results indicate that, for the typical input switching activity of 0.3, DETNKFF reduces power consumption by as much as 21 %. Latency is also improved by about 6 % as compared to the conventional flip-flop. The improvement of power-delay product is also as much as 25 %.

• Proceedings of the KIEE Conference
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• 2009.04a
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• pp.10-12
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• 2009

Electromagnetic Interference(EMI) in electric railway operation has become increasingly important. The components within very high power electronic, and the circuits for treating low-level signals, comprise complex system that must coexist and be highly reliable. To study it, It were included how much the HEMU-400X generates EMI and it has an effect on the power conversion units which resulted from Power Line Disturbance (PLD) phenomenon by contact loss during its running. In this study, the dynamic characteristic of a contact wire and pantograph suppling electrical power to high-speed trains are investigated. The analysis of the loss of contact based on Power Simulator program software is performed to develop power line disturbance model suitable for high speed operation. It is confirmed that a contact wire and pantograph model are necessary for studying the dynamic behavior of the pantograph system.

• Proceedings of the IEEK Conference
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• 1998.10a
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• pp.1093-1096
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• 1998

The architecture and circuit design of low voltage, high performance barrel shifter is proposed in this paper. The proposed architecture consists of two arrays for byte and bit rotate/shift to perform 32-bit operation and is preferred for even bigger data length as it can be adapted for 64-bit extention with no increase of number of stages. NORA logic structure was used for circuit implementation to achieve the best performance in terms of speed, power and area. The complicated cloking control has been resolved with the ingenious design of clock dirver. The circuit simulation results in 3.05ns delay, 9.37㎽ power consumption at 1V, 160MHz operation when its implemented in low power $0.5\mu\textrm{m}$ CMOS technology.

• The Transactions of The Korean Institute of Electrical Engineers
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• v.65 no.4
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• pp.533-538
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• 2016

In a power grid that has a high penetration of wind power, the highly-fluctuating output power of wind turbine generators (WTGs) adversely impacts the power quality in terms of the system frequency. This paper proposes a power smoothing scheme of a variable-speed WTG that can smooth its fluctuating output power caused by varying wind speeds, thereby improving system frequency regulation. To achieve this, an additional loop relying on the frequency deviation that operates in association with the maximum power point tracking control loop, is proposed; its control gain is modified with the rotor speed. For a low rotor speed, to ensure the stable operation of a WTG, the gain is set to be proportional to the square of the rotor speed. For a high rotor speed, to improve the power smoothing capability, the control gain is set to be proportional to the cube of the rotor speed. The performance of the proposed scheme is investigated under varying wind speeds for the IEEE 14-bus system using an EMTP-RV simulator. The simulation results indicate that the proposed scheme can mitigate the output power fluctuation of WTGs caused by varying wind speeds by adjusting the control gain depending on the rotor speed, thereby supporting system frequency regulation.

• International Journal of Fluid Machinery and Systems
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• v.2 no.4
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• pp.334-345
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• 2009

Pumped storage power plants are playing a significant role in the contribution to the stabilization of an electrical grid, above all by stable operation and fast reaction to sudden load respectively frequency changes. Optimized efficiency and smooth running characteristics both in pump and turbine operation, improved stability for synchronization in turbine mode, load control in pump mode operation and also short reaction times may be achieved using adjustable speed power units. Such variable speed power plants are applicable for high variations of head (e.g. important for low head pump-turbine projects). Due to the rapid development of power semiconductors and frequency converter technology, feasible solutions can be provided even for large hydro power units. Suitable control strategies as well as clear design criteria contribute significantly to the optimal usage of the pump turbine and motor-generators. The SIMSEN tool for dynamic simulations has been used for comparative investigations of different configurations regarding the power converter topology, types of semiconductors and types of motor-generators including the coupling to the hydraulic system. A brief overview of the advantages & disadvantages of the different solutions can also be found in this paper. Using this approach, a customized solution minimizing cost and exploiting the maximum usage of the pump-turbine unit can be developed in the planning stage of new and modernization pump storage projects.