• Journal of the Institute of Electronics Engineers of Korea SD
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• v.42 no.2 s.332
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• pp.23-30
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• 2005

This paper describes a DLL(delay locked loop)-based multi-clock generator having the lower active stand-by power as well as a fast relocking after re-activating the DLL. for low power and high speed VLSI chip. It enables a frequency multiplication using frequency multiplier scheme and produces output clocks with 50:50 duty-ratio regardless of the duty-ratio of system clock. Also, digital control scheme using DAC enables a fast relocking operation after exiting a standby-mode of the clock system which was obtained by storing analog locking information as digital codes in a register block. Also, for a clock multiplication, it has a feed-forward duty correction scheme using multiphase and phase mixing corrects a duty-error of system clock without requiring additional time. In this paper, the proposed DLL-based multi-clock generator can provides a synchronous clock to an external clock for I/O data communications and multiple clocks of slow and high speed operations for various IPs. The proposed DLL-based multi-clock generator was designed by the area of $1796{\mu}m\times654{\mu}m$ using $0.35-{\mu}m$ CMOS process and has $75MHz\~550MHz$ lock-range and maximum multiplication frequency of 800 MHz below 20psec static skew at 2.3v supply voltage.

• The Transactions of the Korea Information Processing Society
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• v.1 no.4
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• pp.469-478
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• 1994

In this paper, a high speed, high resolution information processing digital- analog converter was designed for high definition color graphic, digital image signal processing, HDTV. For high speed operation, matrix type current cell array, latch which is not use pipelined, and two dimensional structure decoder using transmission gate were designed. It is adopted to fast-conversion, low-power implementation and exhibited high performance at linearity and accuracy. To reduce silicon area and to maintain resolution, current cell array composed of weighted and non-weighted current cells. In this paper, deglitching current cell design for high accuracy, new switching algorithm assert to reduce switching error. It's This circuit dissipates 130W with a 5-V power supply, and operate above 100MHz with 10 bit resolution.

• Journal of Electrical Engineering and Technology
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• v.13 no.5
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• pp.1956-1964
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• 2018

Since the stator winding of High-Speed Permanent Magnet Generator (HSPMG) has few winding turns and low inductance value, it is more prone to be influenced by harmonic current. Moreover, the operation efficiency and the torque stability of HSPMG will be greatly influenced by harmonic current. Taking a 117 kW, 60 000 rpm HSPMG as an example, in order to analyze the effects of harmonic current on HSPMG in this paper, the 2-D finite element electromagnetic field model of the generator was established and the correctness of the model was verified by testing the generator prototype. Based on the model, the losses and torque of the generator under different frequency harmonic current were studied. The change rules of the losses and torque were found out. Based on the analysis of the influence of the harmonic phase angle on torque ripple, it is found that the torque ripple could be weakened through changing the harmonic phase angle. Through the analysis of eddy current density in rotor, the change mechanism of the rotor eddy current loss was revealed. These conclusions can contribute to reduce harmonic loss, prevent demagnetization fault and optimize torque ripple of HSPMG used in distributed power supply system.

• Journal of the Korea Institute of Information and Communication Engineering
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• v.10 no.2
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• pp.321-327
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• 2006

This paper presents low power and high frequency design of instructions using ad-hoc techniques at transistor level for full custom and semi-custom ASIC(Application Specific Integrated Circuit) designs. The proposed design has been verified at high level using Verilog-HDL and simulated using ModelSim for the logical correctness. It is then observed at the layout level using LASI using $0.25{\mu}m$ technology and analyzed for timing characteristic under Win-spice simulation environment. The result shows the significant reduction up to $35\%$ in the power consumption by any general purpose processor like RISC or CISC. A significant reduction in the propagation delay is also observed. increasing the frequency for the fetch and execute cycle for the CPU, thus increasing the overall frequency of operation.

• Journal of the Institute of Electronics Engineers of Korea SC
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• v.45 no.2
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• pp.26-36
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• 2008

Due to the differential and low voltage swing, Low Voltage Differential Signaling(LVDS) has been widely used for high speed data transmission with low power consumption. This paper proposes new LVDS I/O interface circuits for more than 1.3 Gb/s operation. The LVDS receiver proposed in this paper utilizes a sense amp for the pre-amp instead of a conventional differential pre-amp. The proposed LVDS allows more than 1.3 Gb/s transmission speed with significantly reduced driver output voltage. Also, in order to further improve the power consumption and noise performance, this paper introduces an inductance impedance matching technique which can eliminate the termination resistor. A new form of unfolded impedance matching method has been developed to accomplish the impedance matching for LVDS receivers with a sense amplifier as well as with a differential amplifier. The proposed LVDS I/O circuits have been extensively simulated using HSPICE based on 0.35um TSMC CMOS technology. The simulation results show improved power gain and transmission rate by ${\sim}12%$ and ${\sim}18%$, respectively.

• Journal of the Institute of Electronics Engineers of Korea SC
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• v.42 no.6
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• pp.37-48
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• 2005

The efficiency of power supply circuits such as DC-DC converters and batteries varies on the trend of the power consumption because their efficiencies are not fixed. To analyze the efficiency of power supply circuits, we need the temporal behavior of the power consumption of the loads, which is dependent on the activity factors of the devices during the operation. Since it is not easy to model every detail of those factors, one of the most accurate power consumption analyses of power supply circuits is measurement of a real system, which is expensive and time consuming. In this paper, we introduce an active load emulator for embedded systems which is capable of power measurement, logging, replaying and synthesis. We adopt a pattern recognition technique for data compression in that long-term behaviors of power consumption consist of numbers of repetitions of short-term behaviors, and the number of short-term behaviors is generally limited to a small number. We also devise a heterogeneous structure of active load elements so that low-speed, high-current active load elements and high-speed, low-current active load elements may emulate large amount and fast changing power consumption of digital systems. For the performance evaluation of our load emulator, we demonstrate power measurement and emulation of a hard drive. As an application of our load emulator, it is used for the analysis of a DC-DC converter efficiency and for the verification of a low-power frequency scaling policy for a real-time task.

• Proceedings of the KIEE Conference
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• 1998.11a
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• pp.344-346
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• 1998

The OBCS(On-Board Computer System) achieves train system diagnosis and control. For commercial train operation, it must guarantee the reliability for safe and have low cost operational algorithm. To guarantee the diagnosis function and the control ability of OBCS, sufficient actual railway running test under severe conditions is required. But, running test has some limitations for making severe conditions because of safety and it demands quite long time and a lot of costs. So simulator is required and is utilized in many countries. We designed a simulator to test various functions and performance of controllers for high speed train's power car under various conditions and it is represented briefly.

• ETRI Journal
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• v.39 no.4
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• pp.570-581
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• 2017

Multiplication in finite fields is used in many applications, especially in cryptography. It is a basic and the most computationally intensive operation from among all such operations. Several systolic multipliers are proposed in the literature that offer low hardware complexity or high speed. In this paper, a bit-parallel polynomial basis systolic multiplier for generic irreducible polynomials is proposed based on a modified interleaved multiplication method. The hardware complexity and delay of the proposed multiplier are estimated, and a comparison with the corresponding multipliers available in the literature is presented. Of the corresponding multipliers, the proposed multiplier achieves a reduction in the hardware complexity of up to 20% when compared to the best multiplier for m = 163. The synthesis results of application-specific integrated circuit and field-programmable gate array implementations of the proposed multiplier are also presented. From the synthesis results, it is inferred that the proposed multiplier achieves low power consumption and low area complexitywhen compared to the best of the corresponding multipliers.

• Journal of the Institute of Electronics Engineers of Korea SC
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• v.45 no.2
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• pp.37-44
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• 2008

This paper presents a 5.8 GHz PLL using high-speed ring oscillator for WLAN. The proposed ring oscillator has been designed using the negative skewed delay scheme and for differential mode operation. Therefore, the oscillator is insensitive to power-supply-injected noise, and it has the merit of low 1/f noise because tail current sources are not used. The output frequency ranges from 5.13 to 7.04 GHz with the control voltage varing from 0 to 1.8 V. The proposed PLL circuits have been designed, simulated, and proved using 0.18 um 1.8 V TSMC CMOS library. At the operation frequency of 5.8 GHz, the locking time is 2.5 us and the simulated power consumption is 59.9 mW.

• The Journal of Korean Institute of Communications and Information Sciences
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• v.26 no.12C
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• pp.255-260
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• 2001

This paper describes the design of the Register Controlled DLL(Delay-Locked Loop) that achieves fast locking and low Power consumption using a new locking algorithm. A fashion for a fast locking speed is that controls the two controller in sequence. The up/down signal due to clock skew between a internal and a external clock in phase detector, first adjusts a large phase difference in coarse controller and then adjusts a small phase difference in fine controller. A way for a low power consumption is that only operates one controller at once. Moreover the proposed DLL shows better jitter performance Because using the lock indicator circuit. The proposed DLL circuit is operated from 50MHz to 200MHz by SPICE simulation. The estimated power dissipation is 15mA at 200MHz in 3.3V operation. The locking time is within 7 cycle at all of operating frequency.