• 한국실내디자인학회논문집
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• 제15권3호
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• pp.173-183
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• 2006

Design is inseparably related to aesthetics. In spite of that, it is difficult to explain the precise aesthetic variables that affect the aesthetic value of space or environment. Therefore, this study intended to find the relationships between aesthetic variables by perceptual and affective judgement for space design with focus on complexity and preference variables. The research found low level of 'arousing' as well as high levels of affective dimension variables 'pleasant' and 'relaxing' evoked high preference. High preference also appeared in space design cases with high unity, order, and clarity with low contrast and complexity, which are variables of perceptual dimension. Complexity, one variables of preference by Kaplan, is in an inverse proportion to space preference. Thus, space design with high complexity has high level of 'exciting' and 'arousing' affective responses and relatively low level of 'relaxing' response. Additionally, it was confirmed that the most importantly influential factor on complexity was diverse components rather than visual richness and ornamentation.

• 대한전자공학회:학술대회논문집
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• 대한전자공학회 2006년도 하계종합학술대회
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• pp.533-534
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• 2006

This paper presents the architecture design of a high-speed, low-complexity 128-point radix-$2^4$ FFT processor for ultra-wideband (UWB) systems. The proposed high-speed, low-complexity FFT architecture can provide a higher throughput rate and low hardware complexity by using 2-parallel data-path scheme and single-path delay-feedback (SDF) structure. This paper presents the key ideas applied to the design of high-speed, low-complexity FFT processor, especially that for achieving high throughput rate and reducing hardware complexity. The proposed FFT processor has been designed and implemented with the 0.18-m CMOS technology in a supply voltage of 1.8 V. The throughput rate of proposed FFT processor is up to 1 Gsample/s while it requires much smaller hardware complexity.

• 전기학회논문지
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• 제66권1호
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• pp.153-158
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• 2017

This paper investigates a robust low-complexity design problem for tracking control of uncertain switched pure-feedback systems in the presence of unknown control direction. The completely unknown non-affine nonlinearities are assumed to be arbitrarily switched. By combining the nonlinear error transformation technique and Nussbaum-type functions, a robust tracking controller is designed without using any adaptive function approximators. Thus, compared with existing results, the proposed control scheme has the low-complexity property. From Lyapunov stability theory, it is shown that the tracking error remains within the preassigned transient and steady-state error bounds.

• JSTS:Journal of Semiconductor Technology and Science
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• 제13권5호
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• pp.465-472
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• 2013

This paper presents a low-complexity triple-error-correcting parallel Bose-Chaudhuri-Hocquenghem (BCH) decoder architecture and its efficient design techniques. A novel modified step-by-step (m-SBS) decoding algorithm, which significantly reduces computational complexity, is proposed for the parallel BCH decoder. In addition, a determinant calculator and a error locator are proposed to reduce hardware complexity. Specifically, a sharing syndrome factor calculator and a self-error detection scheme are proposed. The multi-channel multi-parallel BCH decoder using the proposed m-SBS algorithm and design techniques have considerably less hardware complexity and latency than those using a conventional algorithms. For a 16-channel 4-parallel (1020, 990) BCH decoder over GF($2^{12}$), the proposed design can lead to a reduction in complexity of at least 23 % compared to conventional architecttures.

• The Journal of the Acoustical Society of Korea
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• 제17권3E호
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• pp.53-57
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• 1998

Spectral information at a speech coder should be quantized with sufficient accuracy to keep perceptually transparent output speech. Spectral information at a low bit rate speech coder is usually transformed into corresponding line spectrum pair parameters and is often quantized with a vector quantization algorithm. As the vector quantization algorithm generally has high complexity in the optimal code vector searching routine, the complexity reduction in that routine is investigated using the ordering property of the line spectrum pair. When the proposed complexity reduction algorithm is applied to the well-known split vector quantization algorithm, the 46% complexity reduction is achieved in the distortion measure compu-tation.

• 한국전산유체공학회지
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• 제11권3호
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• pp.1-7
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• 2006

Euler and Navier-Stokes flow analyses for helicopter rotor in hover were performed as low and high fidelity analysis models respectively for the future multidisciplinary design optimization(MDO). These design-oriented analyses possess several attributes such as variable complexity, sensitivity-computation capability and modularity which analysis models involved in MDO are recommended to provide with. To realize PC-based analyses for both fidelity models, reduction of flow domain was made by appling farfield boundary condition based on 3-dimensional point sink with simple momentum theory and also periodic boundary condition in the azimuthal direction. Correlations of thrust, torque and their sensitivities between low and high complexity models were tried to evaluate the applicability of these analysis models in MDO process. It was found that the low-fidelity Euler analysis model predicted inaccurate sensitivity derivatives at relatively high angle of attack.

• Journal of information and communication convergence engineering
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• 제16권3호
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• pp.142-147
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• 2018

We present a practical design algorithm for quantizers at nodes in distributed systems in which each local measurement is quantized without communication between nodes and transmitted to a fusion node that conducts estimation of the parameter of interest. The benefits of vector quantization (VQ) motivate us to incorporate the VQ strategy into our design and we propose a low-complexity design technique that seeks to assign vector codewords into sets such that each codeword in the sets should be closest to its associated local codeword. In doing so, we introduce new distance metrics to measure the distance between vector codewords and local ones and construct the sets of vector codewords at each node to minimize the average distance, resulting in an efficient and independent encoding of the vector codewords. Through extensive experiments, we show that the proposed algorithm can maintain comparable performance with a substantially reduced design complexity.

• 한국경영과학회지
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• 제17권2호
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• pp.45-54
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• 1992

It become increasingly important to design user interface to carry low complexity. The cognitive limitations of users severely restrict utility of highly intelligent but complex modern systems. Since humans are known to use schemas to reduce cognitive complexity, imposing good consistency to an interface design that may help that user form useful schemas will provide powerful control over the complexity. This present a research effort to develop a quantitative method for evaluating interface complexity that the user would experience planning his or her course of action. Taking into account the user's potential schemas, a quantitative measure based on information theory was develped to assess the navigational complexity. This approach does not rely on the subjective judgment of the researcher as most schemes dealing with user schemas do. The proposed method may benefit the rapid prototyping approach to design a better user interface by allowing handy assessment of the design.

• 대한전자공학회:학술대회논문집
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• 대한전자공학회 2003년도 하계종합학술대회 논문집 V
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• pp.2633-2636
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• 2003

This study focuses on the new hardware design of fast and low-complexity multiplier over GF(2$\^$m/). The proposed multiplier based on the irreducible all one polynomial (AOP) of degree m, to reduced the system's complexity. It composed of Cyclic Shift, Partial Product, and Modular Summation Blocks. Also it consists of (m＋1)$^2$2-input AND gates and m(m＋1) 2-input XOR gates. Out architecture is very regular, modular and therefore, well-suited for VLSI implementation.

• 한국통신학회논문지
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• 제33권11C호
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• pp.940-948
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• 2008

본 논문에서는 휴대용 고속 무선 LAN 시스템에 적합한 저전력/저면적 MIMO-OFDM 기저대역 프로세서의 효율적인 하드웨어 구조를 제시한다. 고속 무선 LAN 시스템은 최대 수백 Mbps의 데이터 속도를 처리해야 하기 때문에 높은 시스템 클럭과 다중경로 구조를 사용하게 되는데, 이는 소모 전력과 구현 면적을 상승시키는 결과를 초래한다. 따라서 본 논문에서는 저전력으로 동작하면서도 동시에 하드웨어 부담을 줄인 고속 무선 LAN 시스템용 기저대역 프로세서의 하드웨어 구조를 제시한다. 이를 위해서 비트 병렬 처리 구조로 설계된 송신단 PLCP(TX-PLCP) 프로세서와 연산 복잡도를 효과적으로 감소시킨 심볼 검출기를 제안한다. 제안된 TX-PLCP 프로세서 구조는 비트 병렬 처리를 통해 동작 주파수를 감소시킴으로써 전력소모를 낮추는 효과를 얻을 수 있고, PMD 프로세서에서 가장 큰 면적을 차지하는 심볼 검출기는 수식 변형을 통해서 나눗셈 연산 및 제곱근 연산을 제거함으로써 저면적 설계를 가능하게 한다. 제안된 하드웨어 구조를 적용한 기저대역 프로세서는 Verilog HDL을 통해 설계 및 검증되었으며, 0.18um CMOS 공정을 통해 합성되었다. 합성결과, 병렬처리 구조를 적용한 TX-PLCP 프로세서는 비트 직렬 처리 구조에 비해 약 81% 감소된 전력에서 동작함을 확인하였고, 제안된 심볼 검출기는 나눗셈 및 제곱근 연산을 포함하는 심볼 검출 기법에 비해 약 18% 정도 하드웨어 복잡도가 감소함을 확인하였다.