• 정보처리학회논문지A
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• 제14A권3호
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• pp.147-150
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• 2007

본 논문에서는 작은 점유면적과 저 전력 소모 특성을 갖도록 CPL(Complementary Pass-Transistor Logic) 논리구조의 전가산기에 저 전압 스윙 기술을 적용하여 16$\times$16 비트 병렬 곱셈기를 설계하였다. 회로구성상 CPL 논리구조는 CMOS 논리구조에 비해 NMOS 트랜지스터만을 사용하기 때문에 작은 면적을 소비한다. 저 전압 스윙 기술은 회로에 공급되는 전압보다 낮은 전압 레벨에서 출력 동작을 하여 전력 소모를 감소시키는 기술이다. 본 논문에서는 전가산기의 출력 단에 사용되는 인버터에 저 전압 스윙 기술을 적용하여 저 전력 소모 특성을 갖는 16$\times$16 비트 병렬 곱셈기를 설계하였다 설계한 회로는 17.3%의 전력 소모 감소와 16.5%의 전력소모와 지연시간의 곱(Power Delay) 감소가 이루어졌다.

• 전기학회논문지
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• 제67권11호
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• pp.1512-1516
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• 2018

The power system and control system constantly reveals surge voltage such as switching surge of lighting devices and power conversion devices, operating and stops surge of rotating devices, charge & discharge surge, opening & closing surge of circuit breakers and the like. Such a surge voltages can cause damage or malfunction of the element such as CPU, Memory, semiconductor etc. In the industry, in order to protect the system from the surge voltage, a surge protector with low discharge starting voltage, fast response time, and low capacitance is required, and technical development research for that is ongoing. In this paper, in order to solve the problem of the existing GDT discharge tube not discharging from the transient voltage which is higher than the commercial voltage and lower than the discharge voltage of the discharge element, we have developed a discharge element having the control electrode & control circuit. The discharge element having the control electrode and the control circuit can control the discharge voltage according to the needs of the consumer and can satisfy the requirement of the discharge element and the technology of the surge protector downsizing technology and the surge protection technology. It is judged to be effective for development.

• 전력전자학회:학술대회논문집
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• 전력전자학회 2008년도 하계학술대회 논문집
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• pp.520-522
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• 2008

A novel two-switch active clamp forward converter suitable for high input voltage applications is proposed. The main advantage of the proposed converter, compared to the conventional active forward converters, is that circuit complexity is reduced and the voltage stress of the main switches is effectively clamped to either the input voltage or the clamping capacitor voltage by two clamping diodes without limiting the maximum duty ratio. Also, the clamping circuit does not include additional active switches, so a low cost can be achieved without degrading the efficiency. Therefore, the proposed converter can feature high efficiency and low cost for high input voltage applications. The operational principles, features, and design considerations of the proposed converter are presented in this paper. The validity of this study is confirmed by the experimental results from a prototype with 200W, 375V input, and 12V output.

• ETRI Journal
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• 제37권1호
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• pp.97-106
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• 2015

In this paper, MOS-triggered silicon-controlled rectifier (SCR)-based electrostatic discharge (ESD) protection circuits for mobile application in 3.3 V I/O and SCR-based ESD protection circuits with floating N+/P+ diffusion regions for inverter and light-emitting diode driver applications in 20 V power clamps were designed. The breakdown voltage is induced by a grounded-gate NMOS (ggNMOS) in the MOS-triggered SCR-based ESD protection circuit for 3.3 V I/O. This lowers the breakdown voltage of the SCR by providing a trigger current to the P-well of the SCR. However, the operation resistance is increased compared to SCR, because additional diffusion regions increase the overall resistance of the protection circuit. To overcome this problem, the number of ggNMOS fingers was increased. The ESD protection circuit for the power clamp application at 20 V had a breakdown voltage of 23 V; the product of a high holding voltage by the N+/P+ floating diffusion region. The trigger voltage was improved by the partial insertion of a P-body to narrow the gap between the trigger and holding voltages. The ESD protection circuits for low- and high-voltage applications were designed using $0.18{\mu}m$ Bipolar-CMOS-DMOS technology, with $100{\mu}m$ width. Electrical characteristics and robustness are analyzed by a transmission line pulse measurement and an ESD pulse generator (ESS-6008).

• 전력전자학회:학술대회논문집
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• 전력전자학회 2005년도 전력전자학술대회 논문집
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• pp.93-95
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• 2005

A new energy-recovery- sustain circuit suitable for a Plasma Display Panel(PDP) application is proposed. The proposed circuit features the low device voltage stresses, essential to design a power efficient and low cost PDP driver circuit. The proposed circuit is demonstrated experimentally for driving a 42 inches plasma display panel.

• 한국마린엔지니어링학회:학술대회논문집
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• 한국마린엔지니어링학회 2005년도 전기학술대회논문집
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• pp.1166-1169
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• 2005

This paper describes a new transient voltage suppressor(TVS) with a low insertion loss and a high cut-off frequency to protect antenna circuit from transient voltages. Conventional protection devices have some problems such as a low frequency bandwidth and a high insertion loss. In order to improve these limitations, a coaxal type TVS, which consists of a gas tube is developed. The performance of the proposed transient voltage suppressor is tested by using a combination surge generator specified in IEC 61000-4-5 standard and by using a network analyzer of 40 MHz ${\sim}$ 5 GHz bandwidth. From the experimental results, it is confirmed that the proposed TVS has an enough protection performance in a low insertion loss and a high cut-off frequency.

• 조명전기설비학회논문지
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• 제29권9호
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• pp.59-64
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• 2015

IEC is an international standards which are used in many countries with Europe as the center. IEC standard is introduced in Korea according to WTO/TBT agreements, however until now there are no buildings in Korea which are designed applying IEC standard. Therefore, KEA(Korea Electric Association) is scheduled to construct Korean low voltage electrical installation integration test site which is designed applying IEC standard. In this paper, before being under construction of Korean low voltage electrical installation integration test site, power substation is modeled based on real design parameters and method to select circuit breakers and cables is presented applying IEC standard in the modeled power substation. EMTP(ElctroMagnetic Transient Program) is used for simulation program. EMTP which is power system analysis program is easy to model power system and power substation.

• Transactions on Electrical and Electronic Materials
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• 제18권5호
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• pp.257-260
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• 2017

In this paper, we present the design of a 4.5 V low dropout (LDO) voltage regulator implemented in the 130 nm CMOS process. The design uses a two-stage cascaded operational transconductance amplifier (OTA) as an error amplifier, with a body bias technique for reducing dropout voltages. PMOS is used as a pass transistor to ensure stable output voltages. The results show that the proposed LDO regulator has a dropout voltage of 32.06 mV when implemented in the130 nm CMOS process. The power dissipation is only 1.3593 mW and the proposed circuit operates under an input voltage of 5V with an active area of $703{\mu}m^2$, ensuring that the proposed circuit is suitable for low-power applications.

• 전기전자학회논문지
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• 제19권4호
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• pp.573-582
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• 2015

본 논문은 에너지 하베스팅용 이중 모드 부스트 컨버터 설계에 관한 것이다. 설계된 회로는 에너지 하베스팅에 의해 출력된 작은 전압으로부터 startup 회로를 통해 승압된 전압을 얻는다. 이 전압이 일정 전압 이상이 되면, 전압 감지기에 의해 startup 회로에 공급되는 전압이 차단이 된다. 승압된 전압은 부스트 컨트롤러에 의해 최종적으로 $V_{OUT}$이 된다. 회로는 크게 전하 펌프를 위한 오실레이터, 전하 펌프, 펄스 생성기, 전압 감지기, 부스트 컨트롤러로 구성되어있다. 매그나칩 / SK하이닉스의 $0.18{\mu}m$ CMOS 공정을 사용하였다. 설계된 회로는 테스트 결과 최소 입력 전압은 600mV이며, 출력은 3V이고, startup time은 20ms이다. 제작된 부스트 컨버터의 효율은 load current가 3mA일때, 47%로 측정되었다.

• JSTS:Journal of Semiconductor Technology and Science
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• 제14권6호
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• pp.706-711
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• 2014

A low power 6-bit flash ADC that uses an input voltage range detection algorithm is described. An input voltage level detector circuit has been designed to overcome the disadvantages of the flash ADC which consume most of the dynamic power dissipation due to comparators array. In this work, four digital input voltage range detectors are employed and each input voltage range detector generates the specific clock signal only if the input voltage falls between two adjacent reference voltages applied to the detector. The specific clock signal generated by the detector is applied to turn the corresponding latched comparators on and the rest of the comparators off. This ADC consumes 68.82 mW with a single power supply of 1.2V and achieves 4.3 effective number of bits for input frequency up to 1 MHz at 500 MS/s. Therefore it results in 4.6 pJ/step of Figure of Merit (FoM). The chip is fabricated in 0.13-um CMOS process.