• 조명전기설비학회논문지
• /
• 제24권12호
• /
• pp.100-108
• /
• 2010

A low voltage wire should be used considering that a load used in the end is a low voltage. In regard to these wires, there are needs for research about the wire thickness calculation in accordance with IEC standard because the standardization process for IEC (KS standard) was completed on June 30, 2005, and they stopped producing NEC-standard products by the order from Korean Agency for Technology and Standards under Ministry of Knowledge Economy (former Ministry of Commerce, Industry and Energy) since July 1, 2006. This study compared, in terms of the thickness calculation of low voltage wire, a reduction factor application by IEC standard about allowed current and an application for calculation of voltage drop. It also proposed the formula for IEC standard to decrease errors and resolve the difficulty of standardized calculation by analyzing the difference between simplified formula and standardized formula that are the most frequently used calculation method of voltage drop.

• JSTS:Journal of Semiconductor Technology and Science
• /
• 제14권1호
• /
• pp.70-82
• /
• 2014

A nano-power CMOS voltage reference is proposed in this paper. Through a combination of switched-capacitor technology with the body effect in MOSFETs, the output voltage is defined as the difference between two gate-source voltages using only a single PMOS transistor operated in the subthreshold region, which has low sensitivity to the temperature and supply voltage. A low output, which breaks the threshold restriction, is produced without any subdivision of the components, and flexible trimming capability can be achieved with a composite transistor, such that the chip area is saved. The chip is implemented in $0.18{\mu}m$ standard CMOS technology. Measurements show that the output voltage is approximately 123.3 mV, the temperature coefficient is $17.6ppm/^{\circ}C$, and the line sensitivity is 0.15 %/V. When the supply voltage is 1 V, the supply current is less than 90 nA at room temperature. The area occupation is approximately $0.03mm^2$.

• Journal of Electrical Engineering and Technology
• /
• 제12권3호
• /
• pp.1187-1194
• /
• 2017

In this paper, a high step-up DC-DC PWM converter with continuous input current and low voltage stress is presented for renewable energy application. The proposed converter is composed of a boost converter integrated with an auxiliary step-up circuit. The auxiliary circuit uses an additional coupled inductor and a balancing capacitor with voltage doubler and switching capacitor technique to achieve high step-up voltage gain with an appropriate switch duty cycle. The switched capacitors are charged in parallel and discharged in series by the coupled inductor, stacking on the output capacitor. In the proposed converter, the voltage stress on the main switch is clamped, so a low voltage switch with low ON resistance can be used to reduce the conduction loss which results in the efficiency improvement. A detailed discussion on the operating principle and steady-state analyses are presented in the paper. To justify the theoretical analysis, experimental results of a 200W 40/400V prototype is presented. In addition, the conducted electromagnetic emissions are measured which shows a good EMC performance.

• Journal of Power Electronics
• /
• 제14권3호
• /
• pp.468-477
• /
• 2014

This study proposes an optimized design of a dual active bridge converter for a low-voltage charger in a military uninterrupted power supply (UPS) system. The dual active bridge converter is among various bi-directional DC/DC converters that possess a high-efficiency isolated bi-directional converter. In the general design, the zero-voltage switching(ZVS) region is reduced when the battery voltage is high. By contrast, efficiency is low because of high conduction losses when the battery voltage is low. Variable switching frequency is applied to increase the ZVS region and the power conversion efficiency, depending on battery voltage changes. At the same duty, the same power is obtained regardless of the battery voltage using the variable switching frequency. The proposed method is applied to a 5 kW prototype dual active bridge converter, and the experimental results are analyzed and verified.

• IEIE Transactions on Smart Processing and Computing
• /
• 제4권5호
• /
• pp.371-378
• /
• 2015

In this paper, a different type of pulse width modulation (PWM) control scheme for a buck converter is introduced. The proposed buck converter uses PWM with frequency hopping and a low quiescent.current low dropout (LDO) voltage regulator with a power supply rejection ratio enhancer to reduce high spurs, harmonics and output voltage ripples. The low quiescent.current LDO voltage regulator is not described in this paper. A three-bit binary-to-thermometer decoder scheme and voltage ripple controller (VRC) is implemented to achieve low voltage ripple less than 3mV to increase the efficiency of the buck converter. An internal clock that is synchronized to the internal switching frequency is used to set the hopping rate. A center frequency of 2.5MHz was chosen because of the bluetooth low energy (BLE) application. This proposed DC-DC buck converter is available for low-current noise-sensitive loads such as BLE and radio frequency loads in portable communications devices. Thus, a high-efficiency and low-voltage ripple is required. This results in a less than 2% drop in the regulator's efficiency, and a less than 3mV voltage ripple, with -26 dBm peak spur reduction operating in the buck converter.

• 대한전자공학회논문지SD
• /
• 제41권5호
• /
• pp.15-21
• /
• 2004

본 논문에서는 저전력 스위치에 사용되는 소자의 포화전압 특성을 개선하기 위해 새로운 구조의 BJT를 제안하고 있다 기존에 사용되던 finger transistor(FT)의 경우 포화전압이 높아 저전력 소자의 특성을 만족하지 않아 multi base island transistor(MBIT)로 구조를 변경함으로써 저전류 영역에서의 포화전압은 충분히 낮아 저전력용 소자의 특성을 만족하지만, 이 역시 고전류 영역에서는 여전히 포화전압이 높아져 저전력용 소자의 특성을 만족하지 못하는 문제가 발생한다. 이에 본 논문에서는 folded back electrode를 이용한 새로운 구조의 BJT(FBET)를 제안하여 그 특성을 조사하였다. 새로운 구조의 트랜지스터를 적용함으로써 MBIT 구조에 비해 에미터 면적은 35 % 증가하고 접촉창의 면적이 92 % 증가하여, 저 전류 영역에서의 포화 전압은 30 % 감소하였고 고 전류 영역에서의 포화 전압은 에미터 면적 증가와 에미터 접촉 창 면적 증가에 의해 각각 30 %와 7 %씩 감소하여 전체적으로는 37 %가 감소하는 특성을 나타내었다.

• 조명전기설비학회논문지
• /
• 제24권6호
• /
• pp.67-74
• /
• 2010

국내의 저압수용가 대부분은 한국전력공사의 TN-C접지방식으로부터 공급받고 있으나 부하설비는 TT 접지방식을 위주로 한 전기설비기술기준에 따라 시설되어 있다. 본 연구에서는 정보기술설비를 뇌서지로부터 보호할 수 있는 적절한 전원계통접지방식을 제안하기 위해서 TT, TN계통의 뇌서지에 대한 보호성능을 연구하였다. 그 결과, 뇌서지가 배전계통의 중성선에 입사한 때 TT계통의 기기접지단자와 전원선의 중성점 사이에 높은 전위차가 발생하였으며, 예민한 컴퓨터설비가 손상될 위험성이 있으므로 TT계통은 적합하지 않다. 뇌서지로부터 저압 설비를 보호하기 위해서는 등전위본딩이 중요한 요건이며, TN계통이 중성선을 통하여 입사하는 뇌서지의 저감에 가장 우수하였으며, 수용가 인입구에서의 추가접지도 바람직한 방법이다.

• 조명전기설비학회논문지
• /
• 제17권3호
• /
• pp.119-126
• /
• 2003

공항과 같이 간선이 길게 포설될 수 있는 장소의 저압간선 굵기는 해당 케이블의 허용전류와 전력계통의 전압강하를 고려하며 결정된다. 비록 도체의 허용전류 값이 부하의 허용전류 값에 비하여 여유가 있을지라도 계통의 허용전압강하를 고려할 경우 도체의 굵기는 비교적 크게 산정될 수 있다. 이러한 경우에, 도체의 허용전류 값은 부하의 최대전류 값보다 훨씬 크게 산정될 수 있으며 상대적으로 도체에서 발생되는 열은 감소하게 된다. 도체의 최대 허용온도에 보정된 도체의 교류저항 값이 저압간선의 굵기 산정을 위한 전압강하 계산공식에 적용되어 왔으며, 도체의 저항 값은 도체의 실제 온도상승 값이 적용된 저항 값에 비하여 크다 본 연구는 도체의 실제 온도상승 값이 보정된 도체의 저항 값을 적용하여 저압간선 굵기 선정 설계 실무에 적용할 수 있도록 일반적인 계산 방식에 비하여 오차가 적은 경제적인 설계 방식을 연구하였다.

• 전력전자학회:학술대회논문집
• /
• 전력전자학회 2000년도 전력전자학술대회 논문집
• /
• pp.195-198
• /
• 2000

In this paper the insulation characteristics test results of 25 low-voltage induction motors($3\phi$, 5HP, 380V) are presented. Five different types of insulation techniques are applied to 25 motors. The maximum partial discharge (PD) magnitude ($\textrm{Q}_{m}$) discharge inception voltage (DIV) dissipation factor tip-up ($\Delta$tan$\delta$) and rate of change in AC current($\Delta$I) are measured by PD and AC current tests. Also the insulation breakdown tests by high voltage pulse are performed and the corresponding breakdown voltage are obtained.

• ETRI Journal
• /
• 제20권1호
• /
• pp.37-45
• /
• 1998

Reduced surface field lateral double-diffused MOS transistor for the driving circuits of plasma display panel and field emission display in the 120V region have been integrated for the first time into a low-voltage $1.2{\mu}m$ analog CMOS process using p-type bulk silicon. This method of integration provides an excellent way of achieving both high power and low voltage functions on the same chip; it reduces the number of mask layers double-diffused MOS transistor with a drift length of $6.0{\mu}m$ and a breakdown voltage greater than 150V was self-isolated to the low voltage CMOS ICs. The measured specific on-resistance of the lateral double-diffused MOS in $4.8m{\Omega}{\cdot}cm^2$ at a gate voltage of 5V.