• Korean Journal of Applied Biomechanics
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• v.15 no.3
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• pp.95-104
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• 2005

To know the proper setup posture for the various clubs, changes of setup variables according to the change of golf club length was investigated. Swing motions of three male low handicappers including a professional were taken using two high-speed videocameras. Four clubs iron 7, iron 5, iron 3 and driver (wood 1) were selected for this experiment. Three dimensional motion analysis techniques were used to get the kinematical variables. Mathcad and Kwon3D motion analysis program were used to analyze the position, distance and angle data in three dimensions. The variables divided into three categories 1) position and width of anterior-posterior direction 2) position and width of lateral direction 3) angles and evaluated based on the theories of many good golf teachers. Major findings of this study were as follows. 1.The stance (distance between ankle joints) was increased as the length of the club increased but the increasing width was not large. It ranges from 5cm to 10cm and professional player showed small changes. 2. Forward lean angle of trunk was decreased (more erected) as the length of the club increased. It ranges from 30 degrees for iron7 to 25 degrees for driver. 3. Angle between horizontal and right shoulder were increased as the length of the club increased. It ranges from 10 degrees to 20 degrees and professional player showed small changes. 4. Anterior-posterior position of the shoulders were located in front of the foot for all clubs and the difference between the shoulder and knee position was decreased as the length of the club increased. 5. Anterior-posterior position of grip (hand) was located almost beneath the shoulders (2.5cm front) for iron7, but it increased to 10cm for the driver. This grip adjustment makes the height of the posture increased only 5cm from iron7 to driver. 6. Lateral position of grip located at 5cm left for the face of iron7, but it located at the right side (behind) for the face of driver. 7. Lateral position of the ball located at the 40%(15cm) of stance from left ankle for iron7 and located at the 10% (5cm) of stance for driver. 8. Head always located at the right side of the stance and the midpoint of the eyes located at the 37% of stance from the right ankle for all clubs. This means that the axis of swing always maintained consistently for all clubs. 9. Left foot opened to the target for all subject and clubs. The maximum open angle was 25 degrees. Overall result shows that the changes of the setup variables vary only small ranges from iron7 to driver. Paradoxically it could be concluded that the failure of swing result from the excessive changes of setup not from the incorrect changes. These findings will be useful for evaluating the setup motion of golf swing and helpful to most golfers.

• Journal of the Korean Institute of Telematics and Electronics C
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• v.35C no.9
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• pp.64-72
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• 1998

In this paper, the design of a current integrator for low-voltage, low-power, and high frequency applications using complementary high swing cascode current-mirror is presented. The proposed integrator decreases output current errors due to non-zero input resistance and non-infinite output resistance of the simple current integrator. As a design example, the 3rd order Butterworth lowpass filter is designed by a leapfrog method. Also, we apply the predistortion design method to reduce the magnitude distortion which occurs at a cutoff frequency by the undesirable phase shift of a lossless current integrator. The designed current-mode filter is simulated and examined by SPICE using 0.8$\mu\textrm{m}$ CMOS n-well process parameters. The simulation results show 20MHz cutoff frequency and 615㎼ power dissipation with a 2V power supply. And the cutoff frequency of the filters can be easily changed by the DC bias current.

• Journal of the Institute of Electronics Engineers of Korea SD
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• v.43 no.3 s.345
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• pp.21-32
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• 2006

A new SRAM circuit with row-by-row activation and low-swing write schemes is proposed to reduce switching power of active cells as well as leakage one of sleep cells in this paper. By driving source line of sleep cells by $V_{SSH}$ which is higher than $V_{SS}$, the leakage current can be reduced to 1/100 due to the cooperation of the reverse body-bias. Drain Induced Barrier Lowering (DIBL), and negative $V_{GS}$ effects. Moreover, the bit line leakage which may introduce a fault during the read operation can be eliminated in this new SRAM. Swing voltage on highly capacitive bit lines is reduced to $V_{DD}-to-V_{SSH}$ from the conventional $V_{DD}-to-V_{SS}$ during the write operation, greatly saving the bit line switching power. Combining the row-by-row activation scheme with the low-swing write does not require the additional area penalty. By the SPICE simulation with the Berkeley Predictive Technology Modes, 93% of leakage power and 43% of switching one are estimated to be saved in future leakage-dominant 70-un process. A test chip has been fabricated using $0.35-{\mu}m$ CMOS process to verify the effectiveness and feasibility of the new SRAM, where the switching power is measured to be 30% less than the conventional SRAM when the I/O bit width is only 8. The stored data is confirmed to be retained without loss until the retention voltage is reduced to 1.1V which is mainly due to the metal shield. The switching power will be expected to be more significant with increasing the I/O bit width.

• The Journal of Korea Institute of Information, Electronics, and Communication Technology
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• v.13 no.5
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• pp.359-369
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• 2020

In this paper, we proposed a charge pump (CP) circuit that has a wide operating range while reducing the current mismatch for the PLL that generates the main clock of the CMOS X-Ray detector. The operating range and current mismatch of the CP circuit are determined by the characteristics of the current source circuit for the CP circuit. The proposed CP circuit is implemented with a wide operating current mirror bias circuit to secure a wide operating range and a cascode structure with a large output resistance to reduce current mismatch. The proposed wide operating range cascode CP circuit was fabricated as a chip using a 350nm CMOS process, and current matching characteristics were measured using a source measurement unit. At this time, the power supply voltage was 3.3 V and the CP circuit current ICP = 100 ㎂. The operating range of the proposed CP circuit is △VO_Swing=2.7V, and the maximum current mismatch is 5.15 % and the maximum current deviation is 2.64 %. The proposed CP circuit has low current mismatch characteristics and can cope with a wide frequency range, so it can be applied to systems requiring various clock speed.

• Journal of Sensor Science and Technology
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• v.19 no.1
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• pp.25-30
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• 2010

This paper presents a low noise CMOS regulator for a low power capacitive sensor interface in a $0.5{\mu}m$ CMOS standard technology. Proposed LDO regulator circuit consist of a voltage reference block, an error amplifier and a new buffer between error amplifier and pass transistor for a good output stability. Conventional source follower buffer structure is simple, but has a narrow output swing and a low S/N ratio. In this paper, we use a 2-stage wide band OTA instead of source follower structure for a buffer. From SPICE simulation results, we got 0.8 % line regulation and 0.18 % load regulation.

• Proceedings of the Korean Institute of Electrical and Electronic Material Engineers Conference
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• 2009.06a
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• pp.95-96
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• 2009

A fully depleted capacitorless 1-transistor dynamic random access memory (FD 1T-DRAM) based on a sSOI strained-silicon-on-insulator) wafer was investigated. The fabricated device showed excellent electrical characteristics of transistor such as low leakage current, low subthreshold swing, large on/off current ratio, and high electron mobility. The FD sSOI 1T-DRAM can be operated as memory device by the floating body effect when the substrate bias of -15 V is applied, and the FD sSOI 1T-DRAM showed large sensing margin and several milli seconds data retention time.

• Proceedings of the Korean Institute of Electrical and Electronic Material Engineers Conference
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• 1993.11a
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• pp.29-34
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• 1993

In this paper, we used one-dimensional process simulator, SUPREM-II, and two-dimensional device simulator, MINIMOS 4.0 to extract optimal process parameter that can minimize degradation of device characteristics caused by process parameter variation in the case of short channel nMOSFET and pMOSFET device. From this simulation, we have derieved the relationship between process parameter and device characteristics. Here we have presented a method to extract process parameters from design trend curve(DTC) obtained by process and device simulations. We parameters to verify the validity of the DTC method. The experimental result of 0.8 $\mu\textrm{m}$ channel length devices that have been fabricated with optimal that reduces short channel effects, that is, good drain current-voltage characteristics, low body effects and threshold voltage of 1.0 V, high punchthrough and breakdown voltage of 12 V, low subthreshold swing(S.S) values of 105 mV/decade.

• Journal of the Korean Institute of Telematics and Electronics A
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• v.29A no.4
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• pp.33-37
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• 1992

AlGaAs/GaAs quantum well delta-doped channel FET's have been successfully fabricated using by low-pressure metalorganic chemical vapor deposition(LP-MOCVD). The FET's with a gate dimension of 1.8$\mu$m $\times$ 100$\mu$m have a maximum transconductance of 190 mS/mm and a maximum current density of 425 mA/nm. The devices show extremely broad transconductances with a large voltage swing of 2.4V. The S-parameter measurements have indicated that the current gain and power gain cutoff frequencies of the device were 7 and 15 GHz, respectively. These values are among the best performance reported for GaAs based heterojunction FET's with a similar device geometry.

• Journal of the Korean Vacuum Society
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• v.1 no.1
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• pp.212-222
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• 1992

To use polycrystalline Si Thin Film Transistor (poly-Si TFT) in high density SRAM instead of High Load Resistor (HLR), TFT is needed to show good electrical characteristics such as large carrier mobility, low leakage current, high driver current and low subthreshold swing. To satisfy these electrical characteristics, the trap state density must be reduced in the channel poly. Technological issues pertinent to the channel poly fabrication process are investigated and discussed. They are solid phase growth (SPG), Si-ion implantation, laser annealing and hydrogenation. The electrical properties of several CVD oxides used as the gate oxide of TFT are compared. The dependence of the electrical characteristics of TFT on source-drain ion-implantation dose, drain offset length and dopant lateral diffusion are also described.

• Proceedings of the IEEK Conference
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• 2006.06a
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• pp.627-628
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• 2006

A low-voltage switched-capacitor $2^{nd}$-order $\Sigma\Delta$ modulator using full feed-forward is introduced. It has two advantages: the unity signal transfer function and reduced signal swings inside the $\Sigma\Delta$ loop. These features greatly relax the DC gain and output swing requirements for Op-Amp in the low-voltage $\Sigma\Delta$ modulator. Implemented by a 0.18-${\mu}m$ CMOS technology, the $\Sigma\Delta$ modulator satisfies performance requirements for WCDMA and CDMA2000 standards.