• Journal of IKEEE
• /
• v.18 no.4
• /
• pp.586-592
• /
• 2014

In this paper, high efficiency power management IC(PMIC) with DT-CMOS(Dynamic threshold voltage Complementary MOSFET) switching device is presented. PMIC is controlled PWM control method in order to have high power efficiency at high current level. The DT-CMOS switch with low on-resistance is designed to decrease conduction loss. The control parts in Buck converter, that is, PWM control circuit consist of a saw-tooth generator, a band-gap reference(BGR) circuit, an error amplifier, comparator circuit, compensation circuit, and control block. The saw-tooth generator is made to have 1.2MHz oscillation frequency and full range of output swing from supply voltage(3.3V) to ground. The comparator is designed with two stage OP amplifier. And the error amplifier has 70dB DC gain and $64^{\circ}$ phase margin. DC-DC converter, based on current mode PWM control circuits and low on-resistance switching device, achieved the high efficiency nearly 96% at 100mA output current. And Buck converter is designed along LDO in standby mode which fewer than 1mA for high efficiency. Also, this paper proposes two protection circuit in order to ensure the reliability.

• Proceedings of the Korean Institute of Information and Commucation Sciences Conference
• /
• 2007.10a
• /
• pp.761-764
• /
• 2007

This paper addresses the analysis and the design optimization of differential interconnects for Low-Voltage Differential Signaling (LVDS) applications. Thanks to the differential transmission and the low voltage swing, LVDS offers high data rates and improved noise immunity with significantly reduced power consumption in data communications, high-resolution display, and flat panel display. We present an improved model and new equations to reduce impedance mismatch and signal degradation in cascaded interconnects using optimization of interconnect design parameters such as trace width, trace height and πace space in differential flexible printed circuit board (FPCB) transmission lines. We have carried out frequency-domain full-wave electromagnetic simulations, time-domain transient simulations, and S-parameter simulations to evaluate the high-frequency characteristics of the differential FPCB interconnects.

• Proceedings of the Korean Institute of Information and Commucation Sciences Conference
• /
• 2013.10a
• /
• pp.357-360
• /
• 2013

A 1.8V 2-Gb/s scalable low voltage signaling (SLVS) transmitter (TX) is designed for mobile applications requiring high speed and low power consumption. It consists of 4-lane TX for data transmission, 1-lane TX for a source synchronous clocking, and a 8-phase clock generator. The proposed SLVS TX has the scaling voltage swing from 50 mV to 650 mV and supports a high speed (HS) mode and a low power (LP) mode. An output impedance calibration scheme for the SVLS TX is proposed to improve the signal integrity. The proposed SLVS TX is implemented by using a $0.18-{\mu}m$ 1-poly 6-metal CMOS with a 1.8V supply. The simulated data jitter of the implemented SLVS TX is about 8.04 ps at the data rate of 2-Gbps. The area and power consumption of the 1-lane of the proposed SLVS TX are $422{\times}474{\mu}m^2$ and 5.35 mW/Gb/s, respectively.

• Transactions of the Korean Society of Mechanical Engineers B
• /
• v.41 no.8
• /
• pp.505-510
• /
• 2017

This paper presents a low-cost robotic device for shoulder rehabilitation, which is capable of treating various shoulder disabilities. A 3-DOF passive shoulder joint tracking module was designed to allow for translational motion of the shoulder joint center during arm swing, which is essential for natural shoulder movement. The weight of the user's arm and the device were compensated for by springs, to enable gravity-free shoulder motion. In order to reduce the device's cost, only one actuator was used, which can be aligned with the user's shoulder joint in various orientations. The device is capable of implementing five representative shoulder motions, including flexion/extension, abduction/adduction, horizontal abd/adduction, internal/external rotation, and oblique raise. The proposed low-cost shoulder rehabilitation robot is expected to provide effective rehabilitation for patients with various shoulder impairments.

• Journal of Electrical Engineering and Technology
• /
• v.9 no.5
• /
• pp.1654-1659
• /
• 2014

Tunneling field-effect transistors (TFETs) are very applicable to low standby-power application by their virtues of low off-current ($I_{off}$) and small subthreshold swing (S). However, low on-current ($I_{on}$) of silicon-based TFETs has been pointed out as a drawback. To improve $I_{on}$ of TFET, a gate-all-around (GAA) TFET based on III-V compound semiconductor with InAs/InGaAs/InP multiple-heterojunction structure is proposed and investigated. Its performances have been evaluated with the gallium (Ga) composition (x) for $In_{1-x}Ga_xAs$ in the channel region. According to the simulation results for $I_{on}$, $I_{off}$, S, and on/off current ratio ($I_{on}/I_{off}$), the device adopting $In_{0.53}Ga_{0.47}As$ channel showed the optimum direct-current (DC) performance, as a result of controlling the Ga fraction. By introducing an n-type InGaAs thin layer near the source end, improved DC characteristics and radio-frequency (RF) performances were obtained due to boosted band-to-band (BTB) tunneling efficiency.

• Journal of the Korean Applied Science and Technology
• /
• v.37 no.5
• /
• pp.1190-1199
• /
• 2020

The purpose of this study is to analyze the variables affecting the effective stroke in the swing performed through 12 weeks of training for golf beginners, and to provide basic data on the effective stroke factors for the golf beginners to settle on the fairway. Twenty subjects were participate in the study (age: 21.35±1.69 yrs, height: 176.75±7.99 cm, weight: 70.70±9.76 kg). All subjects were subjected to a 12-week golf training, and trackman 4 was used in the 12th week to calculate variables affecting the effective stroke during a golf swing. Trackman data was divided into club-variables and ball-variables, and a binary logistic regression analysis was performed to find out the variables affecting effective strokes. In club-variables, high dynamic loft and low face angles were found in effective stroke, and in ball-variables, fast ball speed, large smash factor, high launch angle, and many spin rates were also found in effective stroke. As a result of the binary logistic regression analysis of club-variables, the probability of an effective stroke increased as the club speed and dynamic loft increased, and the probability of an effective stroke decreased as the face angle increased. The influence of effective stroke in the club-variables was in the order of dynamic loft, face angle, and club speed. In the ball-variable, the probability of an effective stroke increased when the lunch angle increased, and the probability of an effective stroke decreased as the lunch direction increased. As a condition to increase the probability of effective stroke based on the results, it is necessary to increase the club speed through high dynamic loft and low face angle during swing through continuous practice. Through this, the probability of effective stroke through increasing the launch angle and decreasing the launch direction will increase.

• Journal of Information Display
• /
• v.6 no.2
• /
• pp.16-18
• /
• 2005

Hybrid insulator pentacene thin film transistors (TFTs) are fabricated with thermally grown oxide and cross-linked polyvinylalcohol (PVA) including surface treatment by dilute ploymethylmethacrylate (PMMA) layer on $n^+$ doped silicon wafer. Through the optimization of $SiO_2$ layer thickness in hybrid insulator structure, carrier mobility is increased to more than 35 times than that of the TFT which has only a gate insulator of $SiO_2$ at the same electric field. The carrier mobility of $1.80cm^2$/V-s, subthreshold swing of 1.81 V/decade, and $I_{on}/I_{off}$ current ratio> $1.10{\times}10^5$ are obtained less than -30 V bias condition. The result is one of the best reported performances of pentacene TFTs with hybrid insulator including cross-linked PVA layer as a gate insulator at relatively low voltage operation.

• JSTS:Journal of Semiconductor Technology and Science
• /
• v.12 no.2
• /
• pp.168-174
• /
• 2012

This paper describes a novel global on-chip interconnect scheme, in which a one UI-delayed symbol as well as the current symbol is sent for easing the sensing operation at receiver end. With this approach, the voltage swing on the channel for reliable sensing can be reduced, resulting in performance improvement in terms of power consumption, peak current, and delay spread due to PVT variations, as compared to the conventional repeater insertion schemes. Evaluation for on-chip interconnects having various lengths in a 130 nm CMOS process indicated that the proposed on-chip interconnect scheme achieved a power reduction of up to 71.3%. The peak current during data transmission and the delay spread due to PVT variations were also reduced by as much as 52.1% and 65.3%, respectively.

• JSTS:Journal of Semiconductor Technology and Science
• /
• v.17 no.2
• /
• pp.192-198
• /
• 2017

In this paper, we propose a novel double gate vertical channel tunneling field effect transistor (DVTFET) with a dielectric sidewall and optimization characteristics. The dielectric sidewall is applied to the gate region to reduced ambipolar voltage ($V_{amb}$) and double gate structure is applied to improve on-current ($I_{ON}$) and subthreshold swing (SS). We discussed the fin width ($W_S$), body doping concentration, sidewall width ($W_{side}$), drain and gate underlap distance ($X_d$), source doping distance ($X_S$) and pocket doping length ($X_P$) of DVTFET. Each of device performance is investigated with various device parameter variations. To maximize device performance, we apply the optimum values obtained in the above discussion of a optimization simulation. The optimum results are steep SS of 32.6 mV/dec, high $I_{ON}$ of $1.2{\times}10^{-3}A/{\mu}m$ and low $V_{amb}$ of -2.0 V.

• Journal of the Korean Institute of Electrical and Electronic Material Engineers
• /
• v.33 no.1
• /
• pp.16-20
• /
• 2020

In this study, a patterning method using self-aligned nanostructures was introduced to fabricate GaN-based fin-gate HEMTs with normally-off operation, as opposed to high-cost, low-productivity e-beam lithography. The honeycomb-shaped fin-gate channel width is approximately 40~50 nm, which is manufactured with a fine width using a proposed method to obtain sufficient fringing field effect. As a result, the threshold voltage of the fabricated device is 0.6 V, and the maximum normalized drain current and transconductance of Gm are 136.4 mA/mm and 99.4 mS/mm, respectively. The fabricated devices exhibit a smaller sub-threshold swing and higher Gm peak compared to conventional planar devices, due to the fin structure of the honeycomb channel.