• Journal of the Korean Society of Physical Medicine
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• v.3 no.3
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• pp.177-183
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• 2008

Purpose : The purpose of this study was to investigate characteristics of the muscle activities during level walking and stairs ascending in young adults. Methods : Fifteen young adult were recruited this study. Muscle activity (BIOPAC System Inc., Santa Barbara, U.SA). Statistical analysis was difference between level and stair walking. Results : In stance phase, muscle activity of low extremity generally more increased during ramp ascent both young adults. In swing phase, muscle activity of low extremity generally more increased during stairs ascent in young adults. Conclusion : These results indicate that stair and ramp ascent is more difficult task than level walking in young adults. Muscle activity was more changed at ramp ascent. In the future, we suggest that studies of stair and ramp gait pattern regarding ambulatory patient with disabilities be further studied and an appropriate stairs and ramp inclination will be indicated.

• Nuclear Engineering and Technology
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• v.55 no.6
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• pp.1999-2010
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• 2023

Undesirable flapping motion of discs can cause the failure of swing check valves in nuclear passive safety systems. Time-resolved particle image velocimetry (PIV) was employed to investigate the flow characteristics around a free-to-rotate plate and the motion response, with the Reynolds numbers, based on the hydraulic diameter of the channel, from 1.32 × 10⁴ to 3.95 × 10⁴. Appreciable flapping motion (±3.52°) appeared at the Reynolds number of 2.6 × 10⁴ with the frequency of 5.08 Hz. In the low-Reynolds-number case, the plate showed negligible flapping. In the high-Reynolds-number case, the deflection angle increased with reduced flapping amplitude. The torque from the fluid determined the flapping amplitude. In the low-Reynolds-number case, Karman vortices were absent. With increasing Reynolds numbers, Karman vortices developed behind the plate with larger deflection angles. Strong interaction between the wake flow from the leading and trailing edge of the plate was observed. Based on power spectrum density (PSD) analysis, the vortex shedding frequency coincided with the flapping frequency, and the amplitude was positively correlated to the strength of the vortices. Proper orthogonal decomposition (POD) modes evince that, in the case of appreciable motion, coherent structures exhibited a larger spatial scale, enhancing the magnitude of the external torque on the plate.

• Journal of Korea Society of Industrial Information Systems
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• v.18 no.5
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• pp.25-32
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• 2013

A 1.8V 2-Gb/s scalable low voltage signaling (SLVS) transmitter (TX) is designed for mobile applications requiring high speed and low power consumption. It consists of 4-lane TX for data transmission, 1-lane TX for a source synchronous clocking, and a 8-phase clock generator. The proposed SLVS TX has the scaling voltage swing from 50 mV to 650 mV and supports a high speed (HS) mode and a low power (LP) mode. An output impedance calibration scheme for the SVLS TX is proposed to improve the signal integrity. The proposed SLVS TX is implemented by using a 0.18-${\mu}m$ 1-poly 6-metal CMOS with a 1.8 V supply. The simulated data jitter of the implemented SLVS TX is about 8.04 ps at the data rate of 2-Gb/s. The area and power consumption of the 1-lane of the proposed SLVS TX are $422{\times}474{\mu}m^2$ and 5.35 mW/Gb/s, respectively.

• The Journal of the Korea institute of electronic communication sciences
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• v.14 no.6
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• pp.1145-1152
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• 2019

In this paper, a low power current mode 12-bit ADC(: Analog to Digital Converter) is proposed to mix digital circuits and analog circuits with the advantages of low power consumption and high speed operation. The proposed 12 bit ADC is implemented by using 4-bit ADC in a cascade structure, so its power consumption can be reduced, and the chip area can be reduced by using a conversion current mirror circuit. The proposed 12-bit ADC is SK Hynix 350nm process, and post-layout simulation is performed using Cadence MMSIM. It operates at a supply voltage of 3.3V and the area of the proposed circuit is 318㎛ x 514㎛. In addition, the ADC shows the possibility of operating with low power consumption of 3.4mW average power consumption in this paper.

• Journal of the Institute of Electronics and Information Engineers
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• v.49 no.9
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• pp.244-250
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• 2012

This paper describes a 4-Gb/s receiver circuit for a low-swing ground-referenced differential signaling system. The receiver employs a common-gate level-shifter and a continuous linear equalizer which compensates inter-symbol-interference (ISI) and improves voltage and timing margins. A bias circuit maintains the bias current of the level-shifter when the common level of the input signal changes. The receiver is implemented with a low-power 65-nm CMOS technology. When 4-Gb/s 400mVp-p signals are transmitted to the receiver through the channel with the attenuation of -19.7dB, the timing margin based on bit error rate (BER) of $10^{-11}$ is 0.48UI and the power consumption is as low as 0.30mW/Gb/s.

• JSTS:Journal of Semiconductor Technology and Science
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• v.10 no.3
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• pp.176- 184
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• 2010

A low-power inductorless 1:4 DEMUX and a 4:1 MUX for a 90 nm CMOS are presented. The DEMUX can be operated at a speed of 25 Gb/s with the power supply voltage of 1.05 V, and the power consumption is 8.9 mW. The area of the DEMUX core is $29\;{\times}\;40\;{\mu}m^2$. The operation speed of the 4:1 MUX is 13 Gb/s at a power supply voltage of 1.2 V, and the power consumption is 4 mW. The area of the MUX core is $30\;{\times}\;18\;{\mu}m^2$. The MUX/DEMUX mainly consists of differential pseudo-NMOS. In these MUX/DEMUX circuits, logic swing is nearly rail-to-rail, and a low $V_{dd}$. The component circuit is more scalable than a CML circuit, which is commonly used in a high-performance MUX/DEMUX. These MUX/DEMUX circuits are compatible with conventional CMOS logic circuit, and it can be directly connected to CMOS logic gates without logic level conversion. Furthermore, the circuits are useful for core-to-core interconnection in the system LSI or chip-to-chip communication within a multi-chip module, because of its low power, small footprint, and reasonable operation speed.

• Proceedings of the Korean Institute of Electrical and Electronic Material Engineers Conference
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• 2008.11a
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• pp.40-40
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• 2008

$InGaZnO_4$ based thin film transistors (TFTs) are of interest for large area and low cost electronics. The TFTs have strong potential for application in flat panel displays and portable electronics due to their high field effect mobility, high on/off current ratios, and high optical transparency. The application of such room temperature processed transistors, however, is often limited by the operation voltage and long-tenn stability. Therefore, attaining an optimum thickness is necessary. We investigated the thickness dependence of a room temperature grown $MgO_{0.3}BST_{0.7}$ composite gate dielectric and an $InGaZnO_4$ (IGZO) active semiconductor on the electrical characteristics of thin film transistors fabricated on a polyethylene terephthalate (PET) substrate. The TFT characteristics were changed markedly with variation of the gate dielectric and semiconductor thickness. The optimum gate dielectric and active semiconductor thickness were 300 nm and 30 nm, respectively. The TFT showed low operating voltage of less than 4 V, field effect mobility of 21.34 cm2/$V{\cdot}s$, an on/off ratio of $8.27\times10^6$, threshold voltage of 2.2 V, and a subthreshold swing of 0.42 V/dec.

• Journal of the Institute of Electronics Engineers of Korea SD
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• v.46 no.10
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• pp.70-78
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• 2009

This paper addresses the analysis and the design optimization of differential interconnects for high-speed Low-Voltage Differential Signaling (LVDS) applications. Thanks to the differential transmission and the low voltage swing, LVDS offers high data rates and improved noise immunity with significantly reduced power consumption in data communications, high-resolution display, and flat panel display. We present an improved model and new equations to reduce impedance mismatch and signal degradation in cascaded interconnects using optimization of interconnect design parameters such as trace width, trace height and trace space in differential printed circuit board (FPCB) transmission lines. We have carried out frequency-domain full-wave electromagnetic simulations, and time-domain transient simulations to evaluate the high-frequency characteristics of the differential FPCB interconnects. We believe that the proposed approach is very helpful to optimize high-speed differential FPCB interconnects for LVDS applications.

• Korean Journal of Applied Biomechanics
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• v.24 no.4
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• pp.329-338
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• 2014

The purpose of this study was to analyze of the rider postural alignments according to the fitting of stirrups lengths during walk of high level riders. Participants selected as subject were consisted of horse riders of high level (age: $47.66{\pm}3.51yrs$, height: $168.40{\pm}4.84cm$, body weight: $73.36{\pm}15.58kg$, low extremity length: $94.76{\pm}3.98cm$, career: $23.33{\pm}5.77yrs$) and walk with 3 types of stirrup lengths(ratio of low extremity 68.04%, 73.25%, 78.48%). The variables analyzed were consisted of the displacement of Y axis (center of mass, head, thigh, shank and foot), FR angle, LR angle, dynamic postural stability index (DPSI), coefficient of variation (CV%), and distance (X axis) of low extremity limb between right and left. The displacement of Y axis in COM, thigh, shank, foot limbs were not statistically significant, but movements of head showed greater distance of B type and C type than that of A type during 1 stride of walk. The FR and LR angle in trunk of horse rider, dynamic postural stability index and, coefficient of variation didn't show significant difference statistically according to the fitting of stirrup lengths. Also the distance (X axis) of low extremity in thigh and shank didn't show significant difference statistically in between right and left, but right and left foot showed greater distance in C type than that of B and A types during walk in horse back riding. The hip and ankle joint angle not statistically significant according to stirrups lengths, But knee joint angle showed more extended according to the increase of stirrups lengths during stance and swing phase in walk.

• Proceedings of the Korean Institute of Electrical and Electronic Material Engineers Conference
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• 2009.11a
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• pp.5-5
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• 2009

Thin-film-transistors (TFTs) that can be prepared at low temperatures have attracted much attention because of the great potential for transparent and flexible electronics. One of the mainstreams in this field is the use of organic semiconductors such as pentacene. But device performance of the organic TFTs is still limited due to low field-effect mobility and rapid degradation after exposing to air. Alternative approach is the use of amorphous oxide semiconductors as a channel. Amorphous oxide semiconductors (AOSs) based TFTs showed the fast technological development, because AOS films can be fabricated at room temperature and exhibit the possibility in application like flexible display, electronic paper, and larges solar cells. Among the various AOSs, a-IGZO has lots of advantages because it has high channel mobility, uniform surface roughness and good transparency. [1] The high mobility is attributed to the overlap of spherical s-orbital of the heavy post-transition metal cations. This study demonstrated the effect of the variation in channel thickness from 30nm to 200nm on the TFT device performance. When the thickness was increased, turn-on voltage and subthreshold swing was decreased. The a-IGZO channels and source/drain metals were deposited with shadow mask. The a-IGZO channel layer was deposited on $SiO_2$/p-Si substrates by RF magnetron sputtering, where RF power is 150W. And working pressure is 3m Torr, at $O_2/Ar$ (2/28 sccm) atmosphere. The electrodes were formed with electron-beam evaporated Ti (30 nm) and Au (70 nm) bilayer. Finally, Al (150nm) as a gate metal was thermal-evaporated. TFT devices were heat-treated in a furnace at 250 $^{\circ}C$ and nitrogen atmosphere for 1hour. The electrical properties of the TFTs were measured using a probe-station. The TFT with channel thickness of 150nm exhibits a good subthreshold swing (SS) of 0.72 V/decade and on-off ratio of $1{\times}10^8$. The field effect mobility and threshold voltage were evaluated as 7.2 and 8 V, respectively.