• Journal of Power Electronics
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• v.9 no.2
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• pp.259-266
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• 2009

In order to increase the power density of power converters, reduction of the switching losses at high-frequency switching conditions is one of the most important issues. This paper presents a new gate drive circuit that enables the reduction of switching losses in both the Power MOSFET and the IGBT. A distinctive feature of this method is that both the turn-on loss and the turn-off loss are decreased simultaneously without using a conventional ZVS circuit, such as the quasi-resonant adjunctive circuit. Experimental results of the switching loss of both the Power MOSFET and the IGBT are shown. In addition, an energy recovery circuit suitable for use in IGBTs that can be realized by modifying the proposed gate drive circuit is also proposed. The effectiveness of both the proposed circuits was confirmed experimentally by the buck-chopper circuit.

• Proceedings of the KIEE Conference
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• 2002.07b
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• pp.958-960
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• 2002

High Temperature Superconducting (HTS) devices make it possible to operate with no electrical loss by resistance. If, however, the applied current is over its critical current, the phase of HTS devices is changed to normal state, so called, quench. In this case, since resistance of HTS is increased abruptly, it can not be avoidable to damage the whole apparatus. In this study, quench detector to protect HTS devices was proposed. We designed the quench detecting circuit and tested the performance of the circuit. The detecting circuit was consisted of Op-Amp and low pass filter etc, to detect very low voltage around $1{\mu}V$. The circuit detected effectively the low voltage when over current is applied to HTS tapes. At the next step, we are going to apply and test the circuit to protect the prototype HTS cable.

• Journal of Korea Society of Digital Industry and Information Management
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• v.5 no.3
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• pp.69-75
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• 2009

In this paper, we proposed CPLD low power algorithm using reduce glitch power consumption. Proposed algorithm generated a feasible cluster by circuit partition considering the CLB condition within CPLD. Glitch removal process using delay buffer insertion method for feasible cluster. Also, glitch removal process using same method between feasible clusters. The proposed method is examined by using benchmarks in SIS, it compared power consumption to a CLB-based CPLD low power technology mapping algorithm for trade-off and a low power circuit design using selective glitch removal method. The experiments results show reduction in the power consumption by 15% comparing with that of and 6% comparing with that of.

• ETRI Journal
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• v.44 no.3
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• pp.491-503
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• 2022

Metal-oxide-semiconductor field-effect transistors (MOSFETs) are continuously scaling down in the nanoscale region to improve the functionality of integrated circuits. The scaling down of MOSFET devices causes short-channel effects in the nanoscale region. In nanoscale region, leakage current components are increasing, resulting in substantial power dissipation. Very large-scale integration designers are constantly exploring different effective methods of mitigating the power dissipation. In this study, a transistor-level input-controlled stacking (ICS) approach is proposed for minimizing significant power dissipation. A low-power ICS approach is extensively discussed to verify its importance in low-power applications. Circuit reliability is monitored for process and voltage and temperature variations. The ICS approach is designed and simulated using Cadence's tools and compared with existing low-power and high-speed techniques at a 22-nm technology node. The ICS approach decreases power dissipation by 84.95% at a cost of 5.89 times increase in propagation delay, and improves energy dissipation reliability by 82.54% compared with conventional circuit for a ring oscillator comprising 5-inverters.

• Proceedings of the IEEK Conference
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• 1998.10a
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• pp.1093-1096
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• 1998

The architecture and circuit design of low voltage, high performance barrel shifter is proposed in this paper. The proposed architecture consists of two arrays for byte and bit rotate/shift to perform 32-bit operation and is preferred for even bigger data length as it can be adapted for 64-bit extention with no increase of number of stages. NORA logic structure was used for circuit implementation to achieve the best performance in terms of speed, power and area. The complicated cloking control has been resolved with the ingenious design of clock dirver. The circuit simulation results in 3.05ns delay, 9.37㎽ power consumption at 1V, 160MHz operation when its implemented in low power $0.5\mu\textrm{m}$ CMOS technology.

• Proceedings of the IEEK Conference
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• 2002.07c
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• pp.1543-1546
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• 2002

The expandable 4 bit adder/subtracter IC was designed using the adiabatic and dynamic CMOS logic (ADCL) circuit as the ultra-low power consumption basic logic circuit and the IC was fabricated using a standard 1.2 ${\mu}$ CMOS process. As the result the steady operation of 4 bit addition and subtraction has been confirmed even if the frequency of the sinusoidal supply voltage is higher than 10MHz. Additionally, by the simulation, at the frequency of 10MHz, energy consumption per operation is obtained as 93.67pJ (ar addition and as 118.67pJ for subtraction, respectively. Each energy is about 1110 in comparison with the case in which the conventional CMOS logic circuit is used. A simple and low power oscillation circuit is also proposed as the power supply circuit f3r the ADCL circuit. The oscillator operates with a less one volt of DC supply voltage and around one milli-watts power dissipation.

• Proceedings of the IEEK Conference
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• 2004.06b
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• pp.601-604
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• 2004

In this paper, we propose a driving circuit that can be operated with a lower voltage than that of the conventional circuit without reducing the discharge voltage. the circuit proposed in this paper has a merit to improve the electrical characteristics because it can be composed of switching devices with low voltage. The operation and efficiency using real devices. The features of the circuit proposed in this paper are as follows; the power loss can be decreased by the use of low voltage, the cost if the driving circuit for PDP can be reduced by the use of switching devices operated with low voltage.

• Proceedings of the KIEE Conference
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• 2005.05a
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• pp.148-151
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• 2005

This paper proposes a high speed interface using redundant multi-valued logic for high speed communication ICs. This circuit is composed of encoding circuit that serial binary data are received and converted into parallel redundant multi-valued data, and decoding circuit that convert redundant multi-valued data to parallel binary data. Because of the multi-valued data conversion, this circuit makes it possible to achieve higher operating speeds than that of a conventional binary logic. Using this logic, a 1:4 demultiplexer (DEMUX, serial-parallel converter) IC was designed using a 0.35${\mu}m$ standard CMOS Process. Proposed demultiplexer is achieved an operating speed of 3Gb/s with a supply voltage of 3.3V and with power consumption of 48mW. Designed circuit is limited by maximum operating frequency of process. Therefore, this circuit is to achieve CMOS communication ICs with an operating speed greater than 3Gb/s in submicron process of high of operating frequency.

• Journal of the Korean Institute of Illuminating and Electrical Installation Engineers
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• v.25 no.6
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• pp.9-17
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• 2011

The high-power LED (Light Emitting Diode) which is recently gaining popularity as a digital light source has such advantages as low power consumption, long life, fast switching speed, and high efficiency. Thus, many efforts are being made to use the high-power LEDs for general lighting. This paper proposes LED driving circuit uses a DC/DC converter that can recover energy to compensate for the current variations caused by changes in LED equivalent resistance following a temperature change instead of serial resistance. The maximum input voltage of this DC/DC converter has low voltage variations by temperature change when the rated current is formed. In order to return current to the input side, we need a high boosting at low power. Thus, to improve the low efficiency of power converter, the power converter can be configured in such a way to gather the powers of low-capacity DC/DC converters and return the total power. Experiments showed that the proposed system improved efficiency compared to the conventional LED drive using the existing DC/DC converter.

• Proceedings of the Korean Institute of Information and Commucation Sciences Conference
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• 2015.10a
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• pp.477-480
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• 2015

In this paper a low-voltage vibration energy harvesting circuit with MPPT(Maximum Power Point Tracking) control is proposed. By employing bulk-driven technique, the minimum operating voltage of the proposed circuit is as low as 0.8V. The designed MPPT control circuit traces the maximum power point by periodically sampling the open circuit voltage of a full-wave rectifier circuit connected to the piezoelectric device output and delivers the maximum available power to load. The proposed circuit is designed using a $0.35{\mu}m\;CMOS$ process, and the chip area including pads is $1.33mm{\times}1.31mm$. Simulation results show that the maximum power efficiency of the designed circuit is 85.49%.