• 제어로봇시스템학회:학술대회논문집
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• 2003.10a
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• pp.1022-1027
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• 2003

The Motion controllers provide the sophisticated performance and enhanced capabilities we can see in the movements of robotic systems. Several types of motion controllers are available, some based on the kind of overall control system in use. PLC (Programmable Logic Controller)-based motion controllers still predominate. The many peoples use MCU (Micro Controller Unit)-based board level motion controllers and will continue to in the near-term future. These motion controllers control a variety motor system like robotic systems. Generally, They consist of large and complex circuits. PLC-based motion controller consists of high performance PLC, development tool, and application specific software. It can be cause to generate several problems that are large size and space, much cabling, and additional high coasts. MCU-based motion controller consists of memories like ROM and RAM, I/O interface ports, and decoder in order to operate MCU. Additionally, it needs DPRAM to communicate with host PC, counter to get position information of motor by using encoder signal, additional circuits to control servo, and application specific software to generate a various velocity profiles. It can be causes to generate several problems that are overall system complexity, large size and space, much cabling, large power consumption and additional high costs. Also, it needs much times to calculate velocity profile because of generating by software method and don't generate various velocity profiles like arbitrary velocity profile. Therefore, It is hard to generate expected various velocity profiles. And further, to embed real-time OS (Operating System) is considered for more reliable motion control. In this paper, the structure of chip-based precision motion controller is proposed to solve above-mentioned problems of control systems. This proposed motion controller is designed with a FPGA (Field Programmable Gate Arrays) by using the VHDL (Very high speed integrated circuit Hardware Description Language) and Handel-C that is program language for deign hardware. This motion controller consists of Velocity Profile Generator (VPG) part to generate expected various velocity profiles, PCI Interface part to communicate with host PC, Feedback Counter part to get position information by using encoder signal, Clock Generator to generate expected various clock signal, Controller part to control position of motor with generated velocity profile and position information, and Data Converter part to convert and transmit compatible data to D/A converter.

• Journal of Elementary Mathematics Education in Korea
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• v.19 no.3
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• pp.435-455
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• 2015

This study is aimed at analyzing the level change and features of mathematical communication in elementary students' expository writing. 20 students of 5th graders of elementary school in Seoul were given expository writing activity for 14 lessons and their worksheets was analyzed through four categories; the accuracy of the mathematical language, logicality of process and results, specificity of content, achieving the reader-oriented. This study reached the following results. First, The level of expository writing about concepts and principles was gradually improved. But the level of expository writing about problem solving process is not same. Middle class level was lower than early class, and showed a high variation in end class again. Second, features of mathematical communication in expository writing were solidity of knowledge through a mathematical language, elaboration of logic based on the writing, value of the thinking process to reach a result, the clarification of the content to deliver himself and the reader. Therefore, this study has obtained the conclusion that expository writing is worth keeping the students' thinking process and can improve the mathematical communication skills.

• Journal of KIISE:Software and Applications
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• v.35 no.12
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• pp.764-773
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• 2008

The web ontology language(OWL) has become a W3C recommendation to publish and share ontologies on the semantic web. In order to check the satisfiablity of concepts in OWL ontology, OWL reasoners have been introduced. But most reasoners simply report check results without providing a justification for any arbitrary entailment of unsatisfiable concept in OWL ontologies. In this paper, we propose dependency label based causing inconsistency axiom (CIA) detection for debugging unsatisfiable concepts in ontology. CIA is a set of axioms to occur unsatisfiable concepts. In order to detect CIA, we need to find axiom to cause inconsistency in ontology. If precise CIA is gave to ontology building tools, these ontology tools display CIA to debug unsatisfiable concepts as suitable presentation format. Our work focuses on two key aspects. First, when a inconsistency ontology is given, it detect axioms to occur unsatisfiable and identify the root of them. Second, when particular unsatisfiable concepts in an ontology are detected, it extracts them and presents to ontology designers. Therefore we introduce a tableau-based decision procedure and propose an improved method which is dependency label based causing inconsistency axiom detection. Our results are applicable to the very expressive logic SHOIN that is the basis of the Web Ontology Language.

• Smart Media Journal
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• v.7 no.1
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• pp.37-44
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• 2018

Utilizing sequence control and numerical computing, embedded devices are used in a variety of automated systems, including those at industrial sites, in accordance with their control program. Since embedded devices are used as a control system in corporate industrial complexes, nuclear power plants and public transport infrastructure nowadays, deliberate attacks on them can cause significant economic and social damages. Most attacks aimed at embedded devices are data-coded, code-modulated, and control-programmed. The control programs for industry-automated embedded devices are designed to represent circuit structures, unlike common programming languages, and most industrial automation control programs are designed with a graphical language, LAD, which is difficult to process static analysis. Because of these characteristics, the vulnerability analysis and security related studies for industry automation control programs have only progressed up to the formal verification, real-time monitoring levels. Furthermore, the static analysis of industrial automation control programs, which can detect vulnerabilities in advance and prepare for attacks, stays poorly researched. Therefore, this study suggests a method to present a discussion on an industry automation control program designed to represent the circuit structure to increase the efficiency of static analysis of embedded industrial automation programs. It also proposes a medium term translation technology exploiting LLVM IR to comprehensively analyze the industrial automation control programs of various manufacturers. By using LLVM IR, it is possible to perform integrated analysis on dynamic analysis. In this study, a prototype program that converts to a logical expression type of medium language was developed with regards to the S company's control program in order to verify our method.

• Journal of Popular Narrative
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• v.26 no.3
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• pp.9-44
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• 2020

This article aimed to looked back at the 1960s, which were assessed to be 'the age of essays', to survey denotations of essays, amplified by the discourse antagonism surrounding 'essays' and the writings of philosophers. Kim Hyeong Suk, Ahn Byeong Uk, and Kim Te Gil were philosophy professors of Yonsei University, Soongshil University, and Seoul National University and writers of numerous essay collections of the 1960s. However, there have been very few studies conducted on them. This is because of old prejudices within literary history that primarily undervalue essays and practices that try to limit them as 'Literariness'. Essays of the 1960s became the flavor of the times based on democratic demands that attempted to objectify individual experiences and grounds that passed through the war and the April 19 Revolution. The language of philosophers was expropriated through the various senses of first person writing to readers of the times, which lacked civil culture and national morality. Deficits in public spheres of the 1950s and 1960s were filled by Kim Hyeong Suk's narrations of comfort and conquest based on historic experiences, Ahn Byeong Uk's logic of self-discipline and knowledge based on democracy, and Kim Te Gil's humor and introspection that objectified the lives of the petit bourgeois. However, as the essays of philosophers failed to connect with the public discourse of the age, they were unable to go as far as sparking or serving as a medium for civil culture in the 1970s. Regardless, as essays rose historically in the 1960s, thought was given to the characteristics of the 'essay' genre and in connection, to the merits and demerits of cultural history that possesses the language of philosophers.

• The Journal of Korean Institute of Communications and Information Sciences
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• v.30 no.4C
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• pp.283-289
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• 2005

In this paper, we propose two efficient symbol detection algorithms for space-frequency OFDM (SF-OFDM) transmit diversity scheme. When the number of sub-carriers in SF-OFBM scheme is small, the interference between adjacent sub-carriers may be generated. The proposed algorithms eliminate this interference in a parallel or sequential manlier and achieve a considerable performance improvement over the conventional detection algorithm. The bit error rate (BER) performance of the proposed detection algorithms is evaluated by the simulation. In the case of 2 transmit and 2 receive antennas, at $BER=10^{-4}$ the proposed algorithms achieve the gain improvement of about 3 dB. The symbol detectors with the proposed algorithms are designed in a hardware description language and synthesized to gate-level circuits with the $0.18{\mu}m$ 1.8V CMOS standard cell library. With the division-free architecture, the proposed SF-OFDM-PIC and SF-OFDM-SIC symbol detectors can be implemented using 140k and 129k logic gates, respectively.

• Journal of the Institute of Convergence Signal Processing
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• v.4 no.2
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• pp.61-69
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• 2003

In this paper, we developed the U parameter test system which inspects the property of DC parameter for semiconductor products. The developed system is interfaced by IBM-PC. It is consisted of CPLD part, ADC (Analogue to Digital Converter), DAC (Digital to Analogue Converter), voltage/current source, variable resistor and measurement part. In the proposed system, we have designed the constant voltage source and the constant current source in a part. The CPLD part is designed by VHBL, which it generates the control and converts the serial data to parallel data. The proposed system has two test channels and it operates VFCS mode and CFVS mode. The range of test voltage is from 0[V] to 100[V], and the range of test current is from 0[mA] to 100[mA)]. The diode is tested. The test results have a good performance.

• Journal of the Institute of Electronics Engineers of Korea TC
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• v.46 no.6
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• pp.66-77
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• 2009

In this paper, we propose a CORBA middleware extension which is suitable to SCA based communication environment. The extensions guarantee the components to interconnect others without consideration about its implementation way and enables the developers to easily achieve the performance improvements in comparison to the existing methodology. This extension includes the HAO, the IDL2VHDL compiler, and the improvement of ORBit. The HAO is ORB implemented in logic level and is limited the some function according to the characteristic of FPGA. In addition, the IDL2VHDL compiler provides the mapping from CORBA IDL to VHDL, the VHSIC hardware description language, and the additional procedures for processing the component. Finally, the improved ORBit, CORBA ORB on GPP, can be direct connecting with the HAO on FPGA.

• The Transactions of the Korean Institute of Electrical Engineers D
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• v.53 no.1
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• pp.1-9
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• 2004

In this paper, we proposed a hardware(H/W) structure which can compress and recontruct the input image in real time operation and implemented it into a FPGA platform using VHDL(VHSIC Hardware Description Language). All the image processing element to process both compression and reconstruction in a FPGA were considered each of them was mapped into a H/W with the efficient structure for FPGA. We used the DWT(discrete wavelet transform) which transforms the data from spatial domain to the frequency domain, because use considered the motion JPEG2000 as the application. The implemented H/W is separated to both the data path part and the control part. The data path part consisted of the image processing blocks and the data processing blocks. The image processing blocks consisted of the DWT Kernel for the filtering by DWT, Quantizer/Huffman Encoder, Inverse Adder/Buffer for adding the low frequency coefficient to the high frequency one in the inverse DWT operation, and Huffman Decoder. Also there existed the interface blocks for communicating with the external application environments and the timing blocks for buffering between the internal blocks. The global operations of the designed H/W are the image compression and the reconstruction, and it is operated by the unit or a field synchronized with the A/D converter. The implemented H/W used the 54％(12943) LAB(Logic Array Block) and 9％(28352) ESB(Embedded System Block) in the APEX20KC EP20K600CB652-7 FPGA chip of ALTERA, and stably operated in the 70MHz clock frequency. So we verified the real time operation. that is. processing 60 fields/sec(30 frames/sec).

• The Journal of Korean Institute of Communications and Information Sciences
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• v.24 no.7B
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• pp.1393-1399
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• 1999

In this paper, a VLSI design of the convolutional codec chip of code rate r=l/3, and constraint length K=9 is presented, which is able to correct errors of the received data when transmitted data is corrupted in channels. The circuit design mainly aimed for simple implementation. In the decoder, Viterbi algorithm with 3-bit soft-decision is employed. For information sequence updating and storage, the register exchange method is employed, where the register length is 5$\times$K(45 stages). The codec chip is designed using VHDL language and Design Analyzer and VHDL Simulator of Synopsys are used for simulation and synthesis. The chip is composed of ENCODER block, ALIGN block, BMC block, ACS block, SEL_MIN block and REG_EXCH block. The operation of the codec chip is verified though the logic simulations, where several error conditions are assumed. As a result of the timing simulation after synthesis, the decoding speed of 325.5Kbps is achieved, and 6,894 gates is used.