• The Journal of Korean Association of Computer Education
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• v.11 no.2
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• pp.65-78
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• 2008

Many digital logic circuit simulators have been developed for the education on the experiments of digital logic circuits for college or high school students. But the existing simulators have some constraints on the number of inputs of gate, on the display of gate and wire states, and on the number of logic diagrams to be simulated. 1n this paper, we propose a simulator XSIM(eXpandable digital logic circuit SIMulator) which mitigates the constraints and allows multiple diagrams for large scale logics. It is expected that the multiple diagrams on large logics are helpful for team-teaching in school.

• Proceedings of the IEEK Conference
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• 2002.07a
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• pp.220-223
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• 2002

The digital logic systems(DLS) is classified into digital combinational logic systems(CDLS) and digital sequential logic systems(SDLS). This paper presents a method of constructing the digital sequential logic systems without feedback. Firstly we assign all elements in Finite Fields to P-valued digit codes using mathematical properties of Finine Fields. Also, we discuss the operarional properties of the building block T-gate that is used to realizing digital sequential logic systems over Finite Fields. Then we realize the digital sequential logic systems without feedback. This digital sequential logic systems without feedback is constructed ny following steps. Firstly, we assign the states in the state-transition diagram to state P-valued digit dodo, then we obtain the state function and predecessor table that is explaining the relationship between present state and previous states. Next, we obtained the next-state function and predecessor table. Finally, we realize the circuit using T-gate and decoder.

• Journal of the Korean Institute of Illuminating and Electrical Installation Engineers
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• v.21 no.1
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• pp.28-34
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• 2007

In this research, the characteristics of the DC discharge that was the logical gate input of discharge logic gate PDP newly proposed was considered. The logical output is induced by controlling the potential difference of inter-electrode according to the discharge path in the discharge logic gate. From the experimental result the discharge time lag was shortened to 1/3 and the voltage has decreased to 1/2 in the case to apply priming discharge for improving stability of these DC discharges compared with the case when it is not applied. Moreover, after the priming discharge ends, the space charge generated by this discharge influences it up to about $30[{\mu}s]$. And, as a measured result of the influence that the space charge exerts on the DC discharge with the change in time and spatial distance, it has been understood that there is a possibility that going away spatially can slip out the influence of the discharge easily as for going away from the discharge time-wise. Therefore the conclusion that the discharge logic gates of each scanning electrode can be operated independently is obtained.

• The Journal of the Korea institute of electronic communication sciences
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• v.12 no.1
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• pp.189-194
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• 2017

The reversibility of a quantum logic circuit can be realized when two reversible conditions of information reversible and energy reversible circuits are satisfied. In this paper, we have modeled the computation cycle required to recover the information reversibility from the multivalued quantum logic to the original state. For modeling, we used a function embedding method that uses a unitary switch as an arithmetic exponentiation switch. In the quantum logic circuit, if the adjoint gate pair is symmetric, the unitary switch function shows the balance function characteristic, and it takes 1 cycle operation to recover the original information reversibility. Conversely, if it is an asymmetric structure, it takes two cycle operations by the constant function. In this paper, we show that the problem of 2-cycle restoration according to the asymmetric structure when the hybrid MCT gate is realized with the ternary M-S gate can be solved by equivalent conversion of the asymmetric gate to the gate of the symmetric structure.

• Proceedings of the IEEK Conference
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• 2008.06a
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• pp.467-468
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• 2008

In this paper, a logic family, the transmission gate CMOS(TG CMOS) is proposed, which combines the transmission gate and pass transistor resulting in a different configuration from traditional full CMOS. In the simulation, basic cells comprising this logic are designed and their dynamic responses are analyzed. The simulation shows their performance is exceeding that of conventional full CMOS.

• Proceedings of the Optical Society of Korea Conference
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• 2001.02a
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• pp.148-149
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• 2001

순광학적 스위치와 logic gate는 초고속 networks와 컴퓨터를 위한 차세대의 기술로 부각되고 있다. 현재 사용되고 있는 전자적인 switching, routing, 신호 처리들은 대용량 고속화에 그 한계를 나타내고 있다. 미래에 요구되는 초고속 광 네트워크의 계획은 광학 스위치와 광 변조장치가 필요하다는 것을 지적하고있다 최근에 전자나 광전자적으로 가능한 것 이상으로 미래에 요구되는 Tera bits/sec에 접근할 수 있는 고속 연산과 신호처리가 가능한 스위칭에 관한 연구가 활발이 진행되고 있다. (중략)

• Proceedings of the Korean Institute of Information and Commucation Sciences Conference
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• 1999.05a
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• pp.415-419
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• 1999

Many bipolar logic circuit of conventional occurred problem of speed delay according to deep saturation state of vertical NPN Transistor. In order to remove minority carries of the base region at changing signal in conventional bipolar logic circuit, we made transistor which is composed of NPN transistor shortened buried layer under the Base region, PNP transistor which is merged in base, epi layer and substrate. Also the Ring-Oscillator for measuring transmission time-delay per gate was designed as well. The structure of Gate consists of the vertical NPN Transistor, substrate and Merged PNP Transistor. In the result, we fount that tarriers which are coming into intrinsic Base from Emitter and the portion of edge are relatively a lot, so those make Base currents a lot and Gain is low with a few of collector currents because of cutting the buried layer of collector of conventional junction area. Merged PNP Transistor's currents are low because Base width is wide and the difference of Emitter's density and Base's density is small. we get amplitude of logic voltage of 200mv, the minimum of transmission delay-time of 211nS, and the minimum of transmission delay-time per gate of 7.26nS in AC characteristic output of Ring-Oscillator connected Gate.

• Korean Journal of Optics and Photonics
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• v.13 no.2
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• pp.151-154
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• 2002

All-optical OR logic gate is realized by use of gain saturation and wavelength conversion in the semiconductor optical amplifiers (SOA). It is operated by the nonlinearity of the SOA gain and hence to obtain the sufficient gain saturation of the SOA, pump signals are amplified by an Er-doped fiber amplifier (EDFA) at the input of the SOA. The operation characteristics of all-optical OR logic gate are successfully measured at 2.5 Gbit/s.

• JSTS:Journal of Semiconductor Technology and Science
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• v.6 no.3
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• pp.146-153
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• 2006

We have been investigating InGaAs HEMTs as a future high-speed and low-power logic technology for beyond CMOS applications. In this work, we have experimentally studied the role of the side-recess spacing $(L_{side})$ on the logic performance of 50 nm $In_{0.7}Ga_{0.3}As$ As HEMTs. We have found that $L_{side}$ has a large influence on the electrostatic integrity (or short channel effects), gate leakage current, gate-drain capacitance, and source and drain resistance of the device. For our device design, an optimum value of $L_{side}$ of 150 nm is found. 50 nm $In_{0.7}Ga_{0.3}As$ HEMTs with this value of $L_{side}$ exhibit $I_{ON}/I_{OFF}$ ratios in excess of $10^4$, subthreshold slopes smaller than 90 mV/dec, and logic gate delays of about 1.3 ps at a $V_{CC}$ of 0.5 V. In spite of the fact that these devices are not optimized for logic, these values are comparable to state-of-the-art MOSFETs with similar gate lengths. Our work confirms that in the landscape of alternatives for beyond CMOS technologies, InAs-rich InGaAs FETs hold considerable promise.

• Journal of IKEEE
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• v.8 no.1 s.14
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• pp.22-32
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• 2004

In this paper, we proposed MOVAG(Multi Output Value Array Graphs) based on OVAG by Honghai Jiang to construct multiple valued logic function The MDD(Muliple-valued Decision Diagra) needs many processing time and efforts in circuit design for given multi-variable function by D.M.Miller, and we designed a MOVAG which has reduce the data processing time and low complexity. We propose the construction algorithm and input matrix selection algorithm and we designed the multiple-valued logic circuit using T-gate and verified by simulation results.