• Journal of the Korea Institute of Information Security & Cryptology
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• v.24 no.1
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• pp.221-227
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• 2014

When implementing cryptographic algorithms in mobile devices like smart cards, the security against side-channel attacks should be considered. Side-channel attacks try to find critical information from the side-channel infromation obtained from the underlying cryptographic devices' execution. Especially, the power analysis attack uses the power consumption profile of the devices as the side-channel information. This paper proposes a new gate-level countermeasure against the power analysis attack and the glitch attack and suggests how to apply the measure to securely implement AES.

• ETRI Journal
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• v.36 no.1
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• pp.89-98
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• 2014

The integration of digital circuits has a tight relation with the scaling down of silicon technology. The continuous scaling down of the feature size of CMOS devices enters the nanoscale, which results in such destructive effects as short channel effects. Consequently, efforts to replace silicon technology with efficient substitutes have been made. The carbon nanotube field-effect transistor (CNTFET) is one of the most promising replacements for this purpose because of its essential characteristics. Various digital CNTFET-based circuits, such as standard logic cells, have been designed and the results demonstrate improvements in the delay and energy consumption of these circuits. In this paper, a new CNTFET-based 5-input XOR gate based on a novel design method is proposed and simulated using the HSPICE tool based on the compact SPICE model for the CNTFET at the 32-nm technology node. The proposed method leads to improvements in performance and device count compared to the conventional CMOS-style design.

• The Journal of the Korea institute of electronic communication sciences
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• v.9 no.7
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• pp.747-752
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• 2014

This paper relates 10% shrink from $0.13{\mu}m$ design for logic devices as well as input and output (I/O) circuits, different from the previous shrink methodologies which shrink only core device. Thin gate oxide was changed to decoupled plasma nitridation(DPN) oxide as a thin gate oxide (1.2V) to reduce the flicker noise, resulting in three to five times lower flicker noise than pre-shrink process. Unavoidable issue by shrink is capacitor for this normally metal insulator metal (MIM). To solve this issue, 20% higher unit MIM capacitor ($1.2fF/{\mu}m^2$) was developed and its performance were evaluated.

• Journal of the Institute of Electronics Engineers of Korea TC
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• v.39 no.10
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• pp.11-20
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• 2002

This paper proposes a hardware/software codesign of the MLSE equalizer for GSM.GPRS systems. We analyze algorithms of the MLSE equalizer which consists of a channel estimator using the correlation method and the Viterbi processor. We estimate the computational complexity requirement based on the simulation of TI TMS320C5x DSP. We also estimate the gate count from the results of logic synthesis using the samsung 0.5㎛ standard cell library (STD80). Based on the results of the complexity estimation and gate count, we propose the efficient software/hardware codesign of the MLSE equalizer based on the results of the complexity estimation and gate count.

• Journal of the Optical Society of Korea
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• v.5 no.1
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• pp.25-28
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• 2001

By using an XPM (Cross Phase Modulation) wavelength converter, an all-optical AND gate, which is one of six fundamental logic gates, has been demonstrated. The wavelengths for probe and pump signals are 1553.8 and 1545 nm, respectively. First, characteristics of the XPM wavelength converter have been studied. When both probe and pump signals are driven by high power, the output power of the XPM wavelength is high. Based on this fact and the experiment, the all-optical AND gate has been porved. Probe and pump signals are transformed to pulse signals by using Mach-Zehnder modulator, which is induced by a pulse generator. Square pulse signals that are similar to the format of NRZ signals have been generated. By coupling two pulse signals into the XPM wavelength converter, AND characteristics in substantiated.

• The Journal of the Institute of Internet, Broadcasting and Communication
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• v.17 no.2
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• pp.95-104
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• 2017

We investigate the God gate olleh of the largest tomb, pyramid, in the world which is scattered in Jeju Island and construct link which is connecting Jeju people's custom to modern science. The three sacred gates and the two tombs are connected to the olegil space. In this space, the principle of complementarity in which coexistence exist between life and death is hidden in Jeju culture. It is a question and wait. Contrarily, the opposite is complementary. (Contraria Sunt Complementa Latin) This refers to the relationship of each other in relation to one another and in a mutually dependent relationship. Seminal vesicles are used as basic logic in DNA codon of human body as well as communication principle.

• Korean Journal of Optics and Photonics
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• v.14 no.2
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• pp.166-168
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• 2003

By using gain saturation of semiconductor optical amplifiers (SOAs), an all-optical AND gate at 10 Gb/s has been successfully demonstrated. Firstly, Boolean (equation omitted) has been obtained using the first SOA with signal B and clock injection. Then, the all-optical AND gate is achieved using the second SOA with signals A and (equation omitted) injection.

• KIEE International Transaction on Electrical Machinery and Energy Conversion Systems
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• v.5B no.3
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• pp.277-282
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• 2005

This paper describes a step-down AC voltage regulator using an AC chopper and auxiliary transformer, which is a series connected to the main input. The detail design of the AC regulator, logic and PWM pattern of the AC chopper is described and the three-phase AC regulator using two single­phase AC choppers with a three transformer configuration is proposed for three-phase application. The proposed three-phase system has the advantages of lower system cost due to reduced switch number and gate driver circuit as well as advantages of decreased size and weight because it uses a series compensated scheme. The proposed AC regulator has many benefits such as fast voltage control, high efficiency and simple control logic. Experimental results indicate that it can be used as a step-down AC voltage regulator for power saving purposes very efficiently.

• The Journal of the Acoustical Society of Korea
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• v.20 no.1E
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• pp.14-19
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• 2001

We have proposed BIST method and circuit for embedded 16M SDRAM with logic. It can test the AC parameter of embedded 16M SDRAM using the BIST circuit capable of detecting the address of a fail cell installed in an Merged Memory with Logic(MML). It generates the information of repair for redundancy circuit. The function and AC parameter of the embedded memory can also be tested using the proposed BIST method. It is possible to test the embedded SDRAM without external test pin. The total gate of the BIST circuit is approximately 4,500 in the case of synthesizing by 0.25μm cell library and is verified by Verilog simulation. The test time of each one AC parameter is about 200ms using 2Y-March 14n algorithm.

• The Journal of Korean Institute of Communications and Information Sciences
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• v.22 no.11
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• pp.2365-2374
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• 1997

This paper describes two algorithms for technology mapping of multiple output functions into interesting and pupular FPGAs(Field Programmable Gate Array) that use look-yp table memories. For improvement of technology mapping for FPGA, we use the functional decompoition method for multiple output functions. Two algorithms are proposed. The one is the Roth-Karpalgorithm extended for multiple output functions. The other is the efficient algorithm which looks for common decomposition functions through the decomposition procedure. The cost function is used to minimize the number of CLBs and nets and to improve performance of the network. Finally we compare our new algorithm with previous logic design technique. Experimental resutls show sigificant reduction in the number of CLBs and nets.