• 전자공학회논문지C
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• 제35C권8호
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• pp.33-41
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• 1998

We have designed a high speed and low power 16bit-ELM adder with variable-sized cells uitlizing the fact that the logic depth of lower bit position is less than that of the higher bit position int he conventional ELM architecture. As a result of HSPICE simulation with 0.8.mu.m single-poly double-metal LG CMOS process parameter, out 16bit-ELM adder with variable-sized cells shows the reduction of power-delay-product, which is less than that of the conventional 16bit-ELM adder with reference-sized cells by 19.3%. We optimized the desin with various logic styles including static CMOs, pass-transistor logic and Wang's XOR/XNOR gate. Maximum delay path of an ELM adder depends on the implementation method of S cells and their logic style.

• 대한전자공학회논문지
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• 제23권3호
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• pp.327-339
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• 1986

In this paper, a hardware compiler for symbolic description language(SDL) is proposed for logic design automation. Lexical analysis is performed for SDL which describes the behavioral characteristics of a digital system at the register transfer level by the proposed algorithm I. The algorithm I is proposed to get the expressions for the control unit and for the data transfer unit. In order to obtain the network description language(NDL) expressions equivalent to gate-level logic circuits, another algorithm, the the algorithm II, is proposed. Syntax analysis for the data formed by the algorithm I is also Performed using circuit elements such as D Flip-Flop, 2-input AND, OR, and NOT gates. This SDL hardware compiler is implemented in the programming language C(VAX-11/750(UNIX)), and its efficiency is shown by experiments with logic design examples.

• 한국전자통신학회논문지
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• 제11권1호
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• pp.29-36
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• 2016

최근 들어 양자 논리 회로의 저비용 실현 가능성을 가진 $NCV-{\mid}v_1$ >라이브러리라 불리는 새로운 종류의 양자 게이트가 주목을 받고 있다. $NCV-{\mid}v_1$ > MCT 게이트는 입력부에 타깃 입력을 제어하는 $CV-{\mid}v_1$ > 게이트와 정크 비트 제거를 위한 수반 게이트의 종속 AND 구조를 갖는다. 본 논문은 $NCV-{\mid}v_1$ >라이브러리에 대응하는 대칭적 쌍대 특성을 갖는 $NCV^{\dag}-{\mid}v_1$ >라이브러리라 불리는 새로운 게이트를 제안한다. 새로운 $NCV^{\dag}-{\mid}v_1$ >라이브러리는 특정 조건에서 OR 논리로 작동한다. $NCV-{\mid}v_1$ >라이브러리와 $NCV^{\dag}-{\mid}v_1$ >라이브러리를 함께 사용하면 MPMCT 게이트와 SOP 및 POS형 양자논리 회로의 저비용 실현이 가능하며, 순방향과 역방향 연산에 대한 상이한 연산 속성 때문에 듀얼 게이트 성질이 기대된다.

• 한국진공학회:학술대회논문집
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• 한국진공학회 2013년도 제44회 동계 정기학술대회 초록집
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• pp.382-383
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• 2013

Gate-controlled spin-orbit interaction parameter is a key factor for developing spin-Field Effect Transistor (Spin-FET) in a quantum well structure because the strength of the spin-orbit interaction parameter decides the spin precession angle [1]. Many researches show the control of spin-orbit interaction parameter in n-type quantum channels, however, for the complementary logic device p-type quantum channel should be also necessary. We have calculated the spin-orbit interaction parameter and the effective mass using the Shubnikov-de Haas (SdH) oscillation measurement in a GaSb two-dimensional hole gas (2DHG) structure as shown in Fig 1. The inset illustrates the device geometry. The spin-orbit interaction parameter of $1.71{\times}10^{11}$ eVm and effective mass of 0.98 $m^0$ are obtained at T=1.8 K, respectively. Fig. 2 shows the gate dependence of the spin-orbit interaction parameter and the hole concentration at 1.8 K, which indicates the spin-orbit interaction parameter increases with the carrier concentration in p-type channel. On the order hand, opposite gate dependence was found in n-type channel [1,2]. Therefore, the combined device of p- and n-type channel spin transistor would be a good candidate for the complimentary logic device.

• 정보처리학회논문지:컴퓨터 및 통신 시스템
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• 제8권3호
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• pp.57-64
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• 2019

본 논문에서는 이벤트구동 게이트수준 타이밍 시뮬레이션의 성능 향상 및 디버깅 효율성 크게 높일 수 있는 공간적 부분시뮬레이션 전략이 적용된 효율적인 예측기반 병렬 시뮬레이션 기법을 제안한다. 제안된 기법은 병렬 이벤트구동 로컬시뮬레이션들의 입력값과 출력값에 대한 빠르면서도 정확한 예측을 달성하기 위해서, 공간적 부분시뮬레이션 전략을 추상화 상위수준 시뮬레이션에 적용하여 정확한 예측 데이터를 빠르고 즉각적으로 생성해낸다. 공간적 부분시뮬레이션 전략이 적용된 예측기반 병렬 게이트수준 타이밍 시뮬레이션은 성능 평가를 위하여 사용된 6개의 벤치마크 설계들에 대하여 제일 일반적인 순차 이벤트구동 게이트수준 타이밍 시뮬레이션에 비하여 평균 약 3.7배, 상용화된 멀티코어 기반의 병렬 이벤트구동 게이트수준 타이밍 시뮬레이션에 비해서는 평균 9.7배, 그리고 기존의 가장 우수한 예측기반 병렬 이벤트구동 게이트 수준 타이밍 시뮬레이션 결과에 비해서도 평균 2.7배의 시뮬레이션 성능이 향상됨을 확인할 수 있었다.

• Smart Structures and Systems
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• 제14권6호
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• pp.1131-1150
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• 2014

One of the issues in extending the range of applicable problems of real-time hybrid simulation is the computation speed of the simulator when large-scale computational models with a large number of DOF are used. In this study, functionality of real-time dynamic simulation of MDOF systems is achieved by creating a logic circuit that performs the step-by-step numerical time integration of the equations of motion of the system. The designed logic circuit can be implemented to an FPGA-based system; FPGA (Field Programmable Gate Array) allows large-scale parallel computing by implementing a number of arithmetic operators within the device. The operator splitting method is used as the numerical time integration scheme. The logic circuit consists of blocks of circuits that perform numerical arithmetic operations that appear in the integration scheme, including addition and multiplication of floating-point numbers, registers to store the intermediate data, and data busses connecting these elements to transmit various information including the floating-point numerical data among them. Case study on several types of linear and nonlinear MDOF system models shows that use of resource sharing in logic synthesis is crucial for effective application of FPGA to real-time dynamic simulation of structural response with time step interval of 1 ms.

• Journal of Electrical Engineering and Technology
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• 제9권6호
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• pp.1978-1987
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• 2014

Power requirement to the induction heating system varies during the heating process. A closed loop control is required to have a smooth control over the power. In this work, a constant frequency pulse density modulation based power tracking control scheme for domestic induction heating system is developed using the Fuzzy Logic Controller. In the conventional power modulation schemes, the switching losses increase with the change in the load. The proposed pulse density modulation scheme maintains minimum switching losses for the entire load range. This scheme is implemented for the class-D series resonant inverter system. Fuzzy logic controller based power tracking control scheme is developed for domestic induction heating power supply for various power settings. The open loop and closed loop simulation studies are done using the MATLAB/Simulink simulation tool. The control logic is implemented in hardware using the PIC16F877A microcontroller. Fuzzy controller tracks the set power by changing the pulse density of the gate pulses applied to the inverter. The results obtained are used to know the effectiveness of the fuzzy logic controller to achieve the set power.

• Journal of the Optical Society of Korea
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• 제17권5호
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• pp.362-370
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• 2013

In this paper, we propose a novel optical implementation of a 3DES algorithm based on dual XOR logic operations for a cryptographic system. In the schematic architecture, the optical 3DES system consists of dual XOR logic operations, where XOR logic operation is implemented by using a free-space interconnected optical logic gate method. The main point in the proposed 3DES method is to make a higher secure cryptosystem, which is acquired by encrypting an individual private key separately, and this encrypted private key is used to decrypt the plain text from the cipher text. Schematically, the proposed optical configuration of this cryptosystem can be used for the decryption process as well. The major advantage of this optical method is that vast 2-D data can be processed in parallel very quickly regardless of data size. The proposed scheme can be applied to watermark authentication and can also be applied to the OTP encryption if every different private key is created and used for encryption only once. When a security key has data of $512{\times}256$ pixels in size, our proposed method performs 2,048 DES blocks or 1,024 3DES blocks cipher in this paper. Besides, because the key length is equal to $512{\times}256$ bits, $2^{512{\times}256}$ attempts are required to find the correct key. Numerical simulations show the results to be carried out encryption and decryption successfully with the proposed 3DES algorithm.

• Journal of Electrical Engineering and Technology
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• 제4권4호
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• pp.559-565
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• 2009

Power dissipation during scan testing is becoming an important concern as design sizes and gate densities increase. The high switching activity of combinational circuits is an unnecessary operation in scan shift mode. In this paper, we present a novel architecture to reduce test power dissipation in combinational logic by blocking signal transitions at the logic inputs during scan shifting. We propose a unique architecture that uses dmuxed scan flip-flop (DSF) and transmission gate as an alternative to muxed scan flip-flop. The proposed method does not have problems with auto test pattern generation (ATPG) techniques such as test application time and computational complexity. Moreover, our elegant method improves performance degradation and large overhead in terms of area with blocking logic techniques. Experimental results on ITC99 benchmarks show that the proposed architecture can achieve an average improvement of 30.31% in switching activity compared to conventional scan methods. Additionally, the results of simulation with DSF indicate that the powerdelay product (PDP) and area overhead are improved by 28.9% and 15.6%, respectively, compared to existing blocking logic method.

• 대한전기학회:학술대회논문집
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• 대한전기학회 2000년도 추계학술대회 논문집 학회본부 D
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• pp.781-783
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• 2000

1bit full adder have 3 input (including carry_in) and 2 outputs(Sum and Carry_out). Because of 1 bit full adder's propagation delay. We usually use 4-bit binary full adder with fast carry, 74LS283. The 74LS283 is positive logic circuit chip. But the logic function of binary adder is symmetrical, so it can be possible to use it not only positive logic but also the negative logic. This thesis use symmetrical property. such as $C_{i+1}(\bar{a_i}\bar{b_i}\bar{c_i})=C_{i+1}{\bar}(a_i,\;b_i,\;c_i)$ and $S_i(\bar{a_i}\bar{b_i}\bar{c_i})=\bar{S_i}(a_i,\;b_i,\;c_i)$. And prove this property with logic operation. Using these property, the 74LS283 adder is possile as the negation logic circuit. It's very useful to use the chip in negative logic. because many system chip is negative logic circuit. for example when we have negative logic chip with 74LS283. we don't need any not gate for 74LS283 input, and just use output of adder(74LS283) as the negation of original output.