• Journal of Physiology & Pathology in Korean Medicine
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• v.20 no.5
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• pp.1200-1210
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• 2006

This experiment was designed to investigate the effect of the CMT and MCMT hot water extract & ultra-fine powder on microglia and memory deficit model. The effects of the CMT and MCMT hot water extract on expression of IL-l${\beta}$, IL-6, TNF-${\alpha}$, NOS-II, COX-2, IL-10, TGF-${\beta}$1 mRNA and production of IL-lP, IL-6, TNF-a, NO, ROS in BV2 microglial cell line treated by lipopolysacchaide(LPS) ; serum glucose, uric acid, AChE activity of the memory deficit mice induced by scopolamine , behavior of the memory deficit mice induced by scopolamine and were investigated, respectively. The CMT and MCMT hot water extract suppressed the expression of IL-1${\beta}$, IL-6, TNF-${\alpha}$, NOS-II, COX-2 mRNA, production of IL-l${\beta}$, IL-6, TNF-${\alpha}$, NO, ROS and increased the expression of IL-10, TGF-${\beta}$l mRNA in BV2 microglial cell line treated by LPS. The MCMT hot water extract & ultra-fine powder increased glucose, decreased uric acid and AChE significantly in the serum of the memory deficit mice induced by scopolamine. The CMT and MCMT hotwater extract & ultra-fine powder groups showed significantly inhibitory effect on the scopolamine-induced impairment of memory in the experiment of Morris water maze. According to the above result, it is suggested that the CMT and MCMT hot water extract & ultra-fine powder might be usefully applied for prevention and treatment of dementia.

• Journal of Physiology & Pathology in Korean Medicine
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• v.20 no.4
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• pp.997-1008
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• 2006

This experiment was designed to investigate the effect of the CMT and PCMT hot water extract & ultra-fine powder on microglia and memory deficit model. The effects of the CMT and PCMT hot water extract on expression of $IL-l{\beta},\;IL-6,\;TNF-{\alpha}$, NOS-II, COX-2, IL-10, $TGF-{\beta}1$ mRNA and production of $IL-l{\beta},\;IL-6,\;TNF-{\alpha}$, NO, ROS in BV2 microglial cell line treated by lipopolysacchaide(LPS) , serum glucose, uric acid, AChE activity of the memory deficit mice induced by scopolamine , behavior of the memory deficit mice induced by scopolamine and were investigated, respectively. The CMT and PCMT hot water extract suppressed the expression of $IL-l{\beta},\;IL-6,\;TNF-{\alpha}$, NOS-11, COX-2 mRNA, production of $IL-l{\beta},\;IL-6,\;TNF-{\alpha}$, NO, ROS and increased the expression of IL-10, $TGF-{\beta}1$ mRNA in BV2 microglial cell line treated by LPS. The PCMT hot water extract & ultra-fine powder increased glucose, decreased uric acid and AChE significantly in the serum of the memory deficit mice induced by scopolamine. The CMT and PCMT hot water extract & ultra-fine powder groups showed significantly inhibitory effect on the scopolamine-induced impairment of memory in the experiment of Morris water maze. According to the above result, it is suggested that the CMT and PCMT hot water extract & ultra-fine powder might be usefully applied for prevention and treatment of dementia.

• Journal of IKEEE
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• v.5 no.1 s.8
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• pp.43-51
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• 2001

As the density of memories increases, unwanted interference between cells and coupling noise between bit-lines are increased. And testing high-density memories for a high degree of fault coverage can require either a relatively large number of test vectors or a significant amount of additional test circuitry. So far, conventional test algorithms have focused on faults between neighborhood cells, not neighborhood bit-lines. In this paper, a new test algorithm for neighborhood bit-line sensitive faults (NBLSFs) based on the NPSFs(Neighborhood Pattern Sensitive Faults) is proposed. And the proposed algorithm does not require any additional circuit. Instead of the conventional five-cell or nine-cell physical neighborhood layouts to test memory cells, a three-cell layout which is minimum size for NBLSFs detection is used. Furthermore, to consider faults by maximum coupling noise by neighborhood bit-lines, we added refresh operation after write operation in the test procedure(i.e.,$write{\rightarrow}\;refresh{\rightarrow}\;read$). Also, we show that the proposed algorithm can detect stuck-at faults, transition faults, coupling faults, conventional pattern sensitive faults, and neighborhood bit-line sensitive faults.

• Proceedings of the IEEK Conference
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• 2000.11b
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• pp.55-58
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• 2000

This paper describes a single transistor type ferroelectric field effect transistor (1T FeFET) memory celt scheme which can select one unit memory cell and program/read it. To solve the selection problem of 1T FeEET memory cell array, the row direction common well is electrically isolated from different adjacent row direction column. So, we can control voltage of common well line. By applying bias voltage to Gate and Well, respectively, we can implant IT FeEET memory cell scheme which no interface problem and can bit operation. The results of HSPICE simulations showed the successful operations of the proposed cell scheme.

• ETRI Journal
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• v.32 no.4
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• pp.642-644
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• 2010

With the rapid increase occurring in both the capacity and density of memory products, test and repair issues have become highly challenging. Memory repair is an effective and essential methodology for improving memory yield. An SoC utilizes built-in redundancy analysis (BIRA) with built-in self-test for improving memory yield and reliability. This letter proposes a new heuristic algorithm and new hardware architecture for the BIRA scheme. Experimental results indicate that the proposed algorithm shows near-optimal repair efficiency in combination with low area and time overheads.

• ETRI Journal
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• v.43 no.1
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• pp.141-151
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• 2021

Several methods exist for detecting hacking programs operating within online games. However, a significant amount of computational power is required to detect the illegal access of a hacking program in game clients. In this study, we propose a novel detection method that analyzes the protected memory area and the hacking program's process in real time. Our proposed method is composed of a three-step process: the collection of information from each PC, separation of the collected information according to OS and version, and analysis of the separated memory information. As a result, we successfully detect malicious injected dynamic link libraries in the normal memory space.

• Journal of KIISE:Computer Systems and Theory
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• v.30 no.9
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• pp.461-476
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• 2003

Due to the implementation ease and alleviation of memory bottleneck effect, NUMA architecture has dominated in the multiprocessor systems for the past several years. However, because the NUMA system distributes memory in each node, frequent remote memory access is a key factor of performance degradation. Therefore, efficient design of RAC(Remote Access Cache) in NUMA system is critical for performance improvement. In this paper, we suggest Multi-Grain RAC which can adaptively control the RAC line size, with respect to each application behavior Then we simulate NUMA system with multi-grain RAC using MINT, event-driven memory hierarchy simulator. and analyze the performance results. At first, with profile-based determination method, we verify the optimal RAC line size for each application and, then, we compare and analyze the performance differences among NUMA systems with normal RAC, with optimal line size RAC, and with multi-grain RAC. The simulation shows that the worst case can be always avoided and results are very close to optimal case with any combination of application and RAC format.

• Journal of the Korean Institute of Telematics and Electronics A
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• v.31A no.3
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• pp.28-39
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• 1994

We experimented on memory multichip modules to increase the packing density of memory devices and to improve their electrical characteristics. A 128K$\times$8bit SRAM module was made of four 32K$\times$8bit SRAM memory chips. The memory multichip module was constructed on a low-cost double sided PCB(printed circuit boared) substrate. In the process of fabricating a multichip module. we focused on the improvement of its electrical characteristics. volume, and weight by employing bare memory chips. The characteristics of the bare chip module was compared with that of the module with four packaged chips. We conducted circuit routing with a PCAD program, and found the followings: the routed area for the module with bare memory chips reduced to a quarter of that area for module with packaged memory chips. 1/8 in volume, 1/5 in weight. Signal transmission delay times calculated by using transmission line model was reduced from 0.8 nsec to 0.4 nsec only on the module board, but the coupling coefficinet was not changed. Thus, we realized that the electrical characteristics of multichip packages on PCB board be improved greatly when using bare memory chips.

• Journal of Information Processing Systems
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• v.15 no.1
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• pp.151-158
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• 2019

With the recent advances of memory technologies, high-performance non-volatile memories such as non-volatile dual in-line memory module (NVDIMM) have begun to be used as an addition or an alternative to server-side storages. When these memory bus-connected storages (MBSs) are installed over non-uniform memory access (NUMA) servers, the distance between NUMA nodes and MBSs is one of the crucial factors that influence file processing performance, because the access latency of a NUMA system varies depending on its distance from the NUMA nodes. This paper presents the design and implementation of a high-performance logical volume manager for MBSs, called MBS-LVM, when multiple MBSs are scattered over a NUMA server. The MBS-LVM consolidates the address space of each MBS into a single global address space and dynamically utilizes storage spaces such that each thread can access an MBS with the lowest latency possible. We implemented the MBS-LVM in the Linux kernel and evaluated its performance by porting it over the tmpfs, a memory-based file system widely used in Linux. The results of the benchmarking show that the write performance of the tmpfs using MBS-LVM has been improved by up to twenty times against the original tmpfs over a NUMA server with four nodes.

• Journal of KIISE:Computer Systems and Theory
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• v.31 no.8
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• pp.473-486
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• 2004

NUMA systems have remote access caches(RAC) in each local node to reduce the overhead for repeated remote memory accesses. By this RAC, memory latency and network traffic can be reduced and the performance of the multiprocessor system can be improved. Until now, several cache replacement policies have been proposed in recent years, and there also is cache replacement policy for multiprocessor systems. In this paper, we propose a cache replacement policy which is based on cache line coherence information. In this policy, the cache line that does not have an ownership is replaced first with respect to cache line that has an ownership. Like this way, the overhead to transfer ownership is avoided and the memory latency can be decreased. We also propose “Keeping-Ownership replacement policy with MRU (KOM)” and “Keeping-Ownership replacement policy with Reference Bit(KORB)” to reduce the frequent replacement penalty of the ownership-lacking cache line. We compare and analyze these with LRU and Pseudo LRU(PLRU). The simulation shows that KOM outperforms the PLRU by 25%, and KORB outperforms the PLRU by 13%. Although the hardware cost of KOM is very small, the performance of KOM is nearly equal to that of the LRU.