• Phonetics and Speech Sciences
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• v.6 no.2
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• pp.107-114
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• 2014

MDVP and Praat are measured by nine variables in common; F0, jitter local, jitter absolute, jitter relative average perturbation, jitter period perturbation quotient, shimmer local, shimmer dB, shimmer amplitude perturbation quotient, and NHR. In the present study, 30 female subjects were divided by their disorders(control group, vocal nodule group), ages(from 18 to 50 years old), gender(women), and severities of voice disorder(GRBAS-G0, G1, G2). Then, the subjects' vowel /a/ was evaluated by MDVP and Praat. First, jitter and shimmer variables of the MDVP were significantly different by severities. Praat showed different jitter, shimmer, and NHR parameters by severities. Second, jitter and NHR levels of MDVP were meaningfully higher than Praat regardless their severities. The result of the research confirms the relationships among GRBAS, MDVP and Praat as well as the differences in acoustic variables between MDVP and Praat.

• Proceedings of the Korean Institute of Navigation and Port Research Conference
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• v.2
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• pp.385-390
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• 2006

This paper examines the sampling and jitter specifications and considerations for Global Navigation Satellite Systems (GNSS) software receivers. Software radio (SWR) technologies are being used in the implementation of communication receivers in general and GNSS receivers in particular. With the advent of new GPS signals, and a range of new Galileo and GLONASS signals soon becoming available, GNSS is an application where SWR and software-defined radio (SDR) are likely to have an impact. The sampling process is critical for SWR receivers, where it occurs as close to the antenna as possible. One way to achieve this is by BandPass Sampling (BPS), which is an undersampling technique that exploits aliasing to perform downconversion. BPS enables removal of the IF stage in the radio receiver. The sampling frequency is a very important factor since it influences both receiver performance and implementation efficiency. However, the design of BPS can result in degradation of Signal-to-Noise Ratio (SNR) due to the out-of-band noise being aliased. Important to the specification of both the ADC and its clocking Phase- Locked Loop (PLL) is jitter. Contributing to the system jitter are the aperture jitter of the sample-and-hold switch at the input of ADC and the sampling-clock jitter. Aperture jitter effects have usually been modeled as additive noise, based on a sinusoidal input signal, and limits the achievable Signal-to-Noise Ratio (SNR). Jitter in the sampled signal has several sources: phase noise in the Voltage-Controlled Oscillator (VCO) within the sampling PLL, jitter introduced by variations in the period of the frequency divider used in the sampling PLL and cross-talk from the lock line running parallel to signal lines. Jitter in the sampling process directly acts to degrade the noise floor and selectivity of receiver. Choosing an appropriate VCO for a SWR system is not as simple as finding one with right oscillator frequency. Similarly, it is important to specify the right jitter performance for the ADC. In this paper, the allowable sampling frequencies are calculated and analyzed for the multiple frequency BPS software radio GNSS receivers. The SNR degradation due to jitter in a BPSK system is calculated and required jitter standard deviation allowable for each GNSS band of interest is evaluated. Furthermore, in this paper we have investigated the sources of jitter and a basic jitter budget is calculated that could assist in the design of multiple frequency SWR GNSS receivers. We examine different ADCs and PLLs available in the market and compare known performance with the calculated budget. The results obtained are therefore directly applicable to SWR GNSS receiver design.

• The Journal of The Korea Institute of Intelligent Transport Systems
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• v.10 no.4
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• pp.93-99
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• 2011

This paper proposes a novel network jitter estimation algorithm for robust VoIP communication system. The proposed method computes the current network environment mode using the differences of arrival time and generation time from sequential received packets. According to the current network environment mode, the jitter variance weights is adjusted to minimize the error for estimating the network jitter. The jitter average and variance are calculated by the autoregressive estimated algorithm, and then the network jitter is estimated by applying the jitter variance weights.

• The Journal of Korean Institute of Communications and Information Sciences
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• v.35 no.1C
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• pp.40-44
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• 2010

The timing error detector(TED) employed in the closed loop type timing synchronization scheme for an MQASK all digital receiver suffers from the selfnoise-induced timing jitter. To eliminate the timing jitter a prefilter can be added in front of the TED. The prefilter method, however, degrades the stability and timing acquisition performance due to the loop delay and increases the complexity of the synchronizer. This paper proposes a polyphase filter type resampler approach to optimize the performance and architecture of the synchronizer simultaneously. The proposed scheme uses two resamplers which performs matched filtering and matched prefiltering so that the loop delay is minimized with minimal hardware resources. Simulation results showed an excellent acquisition performance with reduced timing jitter.

• Phonetics and Speech Sciences
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• v.12 no.4
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• pp.73-80
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• 2020

In this study, a method for measuring the jitter component in continuous speech is presented. In the conventional jitter measurement method, pitch variabilities are commonly measured from the sustained vowels. In the case of continuous speech, such as a spoken sentence, distortion occurs with the existing measurement method owing to the influence of prosody information according to the sentence. Therefore, we propose a method to reduce the pitch fluctuations of prosody information in continuous speech. To remove this pitch fluctuation component, a curve representing the fluctuation is obtained via polynomial interpolation for the pitch track in the analysis interval, and the shift is removed according to the curve. Subsequently, the variability of the pitch frequency is obtained by a method of measuring jitter from the trajectory of the pitch from which the shift is removed. To measure the effects of the proposed method, parameter values before and after the operations are compared using samples from the Kay Pentax MEEI database. The statistical analysis of the experimental results showed that jitter components from the continuous speech can be measured effectively by proposed method and the values are comparable to the parameters of sustained vowel from the same speaker.

• Journal of IKEEE
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• v.3 no.1 s.4
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• pp.126-132
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• 1999

The SDH (Synchronous Digital Hierarchy) has been rapidly acknowledged as a world wide transmission standard replacing the existing PDH infrastructure. A bit stuffing is used for synchronization between a PDH signal and a SDH node, and a pointer justification is used for synchronization between one SDH node and the other SDH node. During above processes - a bit stuffing and a pointer processing -, a stuffing jitter and a pointer Jitter are produced and the generated jitter can cause transmission error. In this study, a stuffing jitter and a pointer jitter are modeled and analyzed. A Sigma-Delta modulation is described and an advanced jitter reduction technique using a Sigma-Delta modulation technique in the Synchronizer, Pointer Processor and Desynchronizer is provided.

• Journal of the Institute of Electronics and Information Engineers
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• v.50 no.12
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• pp.33-39
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• 2013

There have been studies in improving jitter characteristic of delay locked loop (DLL) even it has a shorter jitter that of phase locked loop (PLL). These studies result in numerous architectures of DLL which improve jitter performance. The paper shows that the jitter characteristic can be improved with various loop filters in DLL. It has been designed with 1.8V $0.18{\mu}m$ CMOS process.

• JSTS:Journal of Semiconductor Technology and Science
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• v.8 no.3
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• pp.193-199
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• 2008

A combined clock and data recovery (CDR) circuit with adaptive cancellation of data-dependent jitter (DDJ) is constructed in all-digital architecture which is amenable to deep submicron technology. The DDJ canceller uses an adaptive FIR filter to compen-sate for any unknown channel characteristic. The proposed CDR decreases jitter in the recovered clock since the DDJ canceller significantly cancels out incoming jitter caused by inter-symbol interference.

• The Journal of Korean Institute of Communications and Information Sciences
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• v.15 no.5
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• pp.353-363
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• 1990

This paper analyzes effect of Data Bit Jitter(DBJ) on the Bit Slip Rate(BSR) of the receiver Data Tracking Loop(DTL). In particular, we point out the characteristic jitter parameters that can be used to estimate the BSR performance for the low frequency parts respectively. We also propose a new format for the DBJ specification, which is more sophisticated than the conventional method but is believed to be more practical and accurate in predicting DBJ effect on the receiver BSR performance. In the proposed method, receive dependent parameters are identified and weighting between different parts of jitter spectrum are properly considered.

• Proceedings of the Korean Institute of Information and Commucation Sciences Conference
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• 2003.10a
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• pp.606-609
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• 2003

It is known that 1/f noise of MOSFET is generated by superposition of single Random Telelgraph Signal (RTS). In this study, jitter from 1/f noise of MOSFET is analysed with RTS supplied to one of the nodes of the ring oscillator under investigation. Jitter rates are investigated as the number of stage, power supply voltage, and the amplitude of RTS change.