• Proceedings of the Korean Vacuum Society Conference
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• 2012.02a
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• pp.144-144
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• 2012

최근 폴리머를 기판으로 하는 고속 Flexible TFT (Thin film transistor)나 고효율의 박막 태양전지(Thin film solar cell)를 실현시키기 위해 낮은 비저항(resistivity)을 가지며, 높은 홀 속도(carrier hall mobility)와 긴 이동거리를 가지는 다결정 반도체 박막(poly-crystalline semiconductor thin film)을 만들고자 하고 있다. 지금까지 다결정 박막 반도체를 만들기 위해서는 비교적 높은 온도에서 장시간의 열처리가 필요했으며, 이는 폴리머 기판의 문제점을 야기시킬 뿐 아니라 공정시간이 길다는 단점이 있었다. 이에 반도체 박막의 재결정화 온도를 낮추어 주는 metal (Al, Ni, Co, Cu, Ag, Pd, etc.)을 이용하여 결정화시키는 방법(MIC)이 많이 연구되어지고 있지만, 이 또한 재결정화가 이루어진 반도체 박막 안에 잔류 금속(residual metal)이 존재하게 되어 비저항을 높이고, 홀 속도와 이동거리를 감소시키는 단점이 있다. 이에 본 실험은, 종래의 MIC 결정화 방법에서 이용되어진 금속 증착막을 이용하는 대신, HIPIMS (High power impulse magnetron sputtering)와 PIII&D (Plasma immersion ion implantation and deposition) 공정을 복합시킨 방법으로 적은 양의 알루미늄을 이온주입함으로써 재결정화 온도를 낮추었을 뿐 아니라, 잔류하는 금속의 양도 매우 적은 다결정 반도체 박막을 만들 수 있었다. 분석 장비로는 박막의 결정화도를 측정하기 위해 GIXRD (Glazing incident x-ray diffraction analysis)와 Raman 분광분석법을 사용하였고, 잔류하는 금속의 양과 화학적 결합 상태를 알아보기 위해 XPS (X-ray photoelectron spectroscopy)를 통한 분석을 하였다. 또한, 표면 상태와 막의 성장 상태를 확인하기 위하여 HRTEM(High resolution transmission electron microscopy)를 통하여 관찰하였다.

• Proceedings of the Korean Institute of Electrical and Electronic Material Engineers Conference
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• 2003.08a
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• pp.93-93
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• 2003

Photoluminescence(PL) properties of Silicon nanocrystals (nc-Si) as a function of temperature is reported to consider the mechanism of PL. Nc-Si has been made by $Si^+$ ion-implantation into thermal $SiO_2$ and subsequent annealing. And after gold had been diffused at the same samples above, the resultant PL spectra has been compared to the PL spectra from the non-gold doped nc-Si. PL peak energy variation from nc-Si is same with the variation of energy bandgap of bulk silicon as temperature changes from 6 K to room temperature. This result may mean nc-Si is still indirect transition material like bulk silicon. Gold doped nc-Si reveals short peak wavelength of PL spectrum than gold undoped one. PL peak shift through gold doing process shows clearly the PL mechanism is not from defect or interface states. PL intensity increases from 6K to a certain temperature and then decrease to room temperature. This characteristic with temperature shows that phonon have a role for the luminescence as theory explains that electron and hole can be recombined radiatively by phonon's assist in nc-Si, which is almost impossible in bulk silicon. Therefore luminescence is observed in nc-Si constructed less than a few of unit cell and the peak energy of luminescence can be higher than the bulk bandgap energy by the bandgap widening effect occurs in nanostructure.

• Journal of the Institute of Electronics Engineers of Korea SD
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• v.38 no.6
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• pp.390-397
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• 2001

A novel self-aligned ESD (Elevated Source Drain) MOSFET structure which can effectively reduce the GIDL (Gate-Induced Drain Leakage) current is proposed and analyzed. The proposed ESD structure is characterized by sidewall spacer and recessed-channel depth which are determined by dry-etching process. Elevation of the Source/Drain extension region is realized so that the low-activation effect caused by low-energy ion implantation can be avoided. Unlike the conventional LDD structures, it is shown that the GIDL current of the ESD structure is suppressed without sacrificing the maximum driving capability. The main reason for the reduction of GIDL current Is the decreased electric field at the point of the maximum band-to-band tunneling as the peak electric field is shifted toward the drain side.

• Journal of the Institute of Electronics Engineers of Korea SD
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• v.47 no.10
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• pp.14-22
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• 2010

The source/channel/drain regions are formed by ion implantation with different dopant types of $n^+/p^{(+)}/n^+$ in the fabrication of the conventional n-type metal-oxide-semiconductor field effect transistor(NMOSFET). In implementing the ultra-small devices with channel length of sub-30 nm, in order to achieve the designed effective channel length accurately, low thermal budget should be considered in the fabrication processes for minimizing the lateral diffusion of dopants although the implanted ions should be activated as completely as possible for higher on-current level. Junctionless (JL) MOSFETs fully capable of the the conventional NMOSFET operations without p-type channel for enlarging the process margin are under researches. In this paper, the optimum design of the JL MOSFET based on silicon nanowire (SNW) structure is carried out by 3-D device simulation and the basic radio frequency (RF) characteristics such as conductance, maximum oscillation frequency($f_{max}$), current gain cut-off frequency($f_T$) for the optimized device. The channel length was 30 run and the design variables were the channel doping concentration and SNW radius. For the optimally designed JL SNW NMOSFET, $f_T$ and $f_{max}$ high as 367.5 GHz and 602.5 GHz could be obtained, respectively, at the operating bias condition $V_{GS}$ = $V_{DS}$ = 1.0 V).

• Journal of the Korean Institute of Telematics and Electronics
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• v.16 no.4
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• pp.36-46
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• 1979

Using N_ Ch silicon gate technology . the capacitors and transistors with various dimenssion were fabricated. Although the applied process was somewhat standard the conditions of ion implantation for the gate were varied by changing the implant energies from 30keV to 60keV for B and from 100 keV to 175keV for P . The doses of the implant also changed from 3 $\times$ 10 /$\textrm{cm}^2$ to 5 $\times$ 10 /$\textrm{cm}^2$ for B and from 4$\times$ 10 /$\textrm{cm}^2$ to 7 $\times$ 10 /$\textrm{cm}^2$ for P . The D. C. parameters such as threshold voltage. substrate doping level, the degree of inversion, capacitance. flat band voltage, depletion layer width, gate oxide thickless, surface states, motile charge density, electron mobility. leakage current were evaluated and also compared with the corresponing theoretical values and / or good numbers for application. The threshold voltages measured using curve tracer and C-V plot gave good agreements with the values calculated from SUPREM II which has been developed by Stanford University process group. The threshold vol tapes with back gate bias were used to calculate the change of the substrate doping level. The measured subthreshold slope enabled the prediction of the degree of inversion The D. C. testing results suggest the realized capacitors and transistors are suited for the memory applications.

• Journal of the Institute of Electronics Engineers of Korea SC
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• v.39 no.6
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• pp.34-42
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• 2002

In this paper, we propose a temperature independent the detective voltage source in voltage detector. The value of a detective voltage source is designed to become m times of silicon bandgap voltage at zero absolute temperature. By properly choosing the temperature coefficient of diode, the temperature coefficient of a concave voltage nonlinearities generated by the ${\Delta}V_{BE}$ section of diode between base and emitter of transistors with a different area can be summed with convex nonlinearities the $V_{BE}$ voltage to achieve the near zero temperature coefficient of the detective voltage source. We designed that the value of a detective voltage can be varied by ${\Delta}V_{BE}$, the $V_{BE}$multiplier circuit and resistor. In order to verify the performance of a proposed detective voltage source, we manufactured the voltage detector IC for 1.9V which is fabricated in $6{\mu}m$ Bipolar technology and measured the operating characteristics, the temperature coefficient of a detective voltage. To reduce the deviation of a detective voltage in the IC process step, we introduced a trimming technology, ion implantation and an isotropic etching. In manufactured IC, the detective voltage source could achieve the stable temperature coefficient of 29ppm/$^{\circ}C$ over the temperature range of -30$^{\circ}C$ to 70$^{\circ}C$. The current consumption of a voltage detector constituted by the proposed detective voltage source is $10{\mu}A$ from 1.9V-supply voltage at room temperature.

• Journal of the Korean Magnetics Society
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• v.14 no.4
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• pp.149-161
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• 2004

The fusion of nano technology and information technology is essential to sustain the present growth rate and to induce new industry in this ever-growing information age. Considering Korean industry whose competitiveness lies heavily on information related technologies, this field will be inevitable for future. Nano materials can be described as novel materials whose size of elemental structure has been engineered at the nanometer scale. Materials in the nanometer size range exhibit fundamentally new behavior, as their size falls below the critical length scale associated with any given property. " Bottom-up' techniques involve manipulating individual atoms and molecules. Bottom-up process usually implies controlled or directed self assembly of atoms and molecules into nano structures. It resembles more closely the processes of biology and chemistry, where atoms and molecules come together to create structures such as crystals or living cells. Nano scale sensors are included in the electronics area since the diverse sensing mechanisms are often housed on a semiconductor substrate and usually give rise to an electronic signal. The application of nano technology to the chemical sensors should allow improvements in functionality such as gas sensing. In this presentation, we will discuss about the nano scale information materials and devices fabricated by using the organic/inorganic nano templates.

• Journal of IKEEE
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• v.23 no.1
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• pp.193-199
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• 2019

In this study, we have proposed a floating metal guard ring structure based on TCAD simulation in order to enhance the breakdown voltage characteristics of gallium oxide ($Ga_2O_3$) vertical high voltage switching Schottky barrier diode. Unlike conventional guard ring structures, the floating metal guard rings do not require an ion implantation process. The locally enhanced high electric field at the anode corner was successfully suppressed by the metal guard rings, resulting in breakdown voltage enhancement. The number of guard rings and their width and spacing were varied for structural optimization during which the current-voltage characteristics and internal electric field and potential distributions were carefully investigated. For an n-type drift layer with a doping concentration of $5{\times}10^{16}cm^{-3}$ and a thickness of $5{\mu}m$, the optimum guard ring structure had 5 guard rings with an individual ring width of $1.5{\mu}m$ and a spacing of $0.2{\mu}m$ between rings. The breakdown voltage was increased from 940 V to 2000 V without degradation of on-resistance by employing the optimum guard ring structure. The proposed floating metal guard ring structure can improve the device performance without requiring an additional fabrication step.

• Proceedings of the Korean Vacuum Society Conference
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• 2016.02a
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• pp.292-292
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• 2016

Transition metal dichalcogenides (TMDs) with a two-dimensional layered structure have been considered highly promising materials for next-generation flexible, wearable, stretchable and transparent devices due to their unique physical, electrical and optical properties. Recent studies on TMD devices have focused on developing a suitable doping technique because precise control of the threshold voltage ($V_{TH}$) and the number of tightly-bound trions are required to achieve high performance electronic and optoelectronic devices, respectively. In particular, it is critical to develop an ultra-low level doping technique for the proper design and optimization of TMD-based devices because high level doping (about $10^{12}cm^{-2}$) causes TMD to act as a near-metallic layer. However, it is difficult to apply an ion implantation technique to TMD materials due to crystal damage that occurs during the implantation process. Although safe doping techniques have recently been developed, most of the previous TMD doping techniques presented very high doping levels of ${\sim}10^{12}cm^{-2}$. Recently, low-level n- and p-doping of TMD materials was achieved using cesium carbonate ($Cs_2CO_3$), octadecyltrichlorosilane (OTS), and M-DNA, but further studies are needed to reduce the doping level down to an intrinsic level. Here, we propose a novel DNA-based doping method on $MoS_2$ and $WSe_2$ films, which enables ultra-low n- and p-doping control and allows for proper adjustments in device performance. This is achieved by selecting and/or combining different types of divalent metal and trivalent lanthanide (Ln) ions on DNA nanostructures. The available n-doping range (${\Delta}n$) on the $MoS_2$ by Ln-DNA (DNA functionalized by trivalent Ln ions) is between $6{\times}10^9cm^{-2}$ and $2.6{\times}10^{10}cm^{-2}$, which is even lower than that provided by pristine DNA (${\sim}6.4{\times}10^{10}cm^{-2}$). The p-doping change (${\Delta}p$) on $WSe_2$ by Ln-DNA is adjusted between $-1.0{\times}10^{10}cm^{-2}$ and $-2.4{\times}10^{10}cm^{-2}$. In the case of Co-DNA (DNA functionalized by both divalent metal and trivalent Ln ions) doping where $Eu^{3+}$ or $Gd^{3+}$ ions were incorporated, a light p-doping phenomenon is observed on $MoS_2$ and $WSe_2$ (respectively, negative ${\Delta}n$ below $-9{\times}10^9cm^{-2}$ and positive ${\Delta}p$ above $1.4{\times}10^{10}cm^{-2}$) because the added $Cu^{2+}$ ions probably reduce the strength of negative charges in Ln-DNA. However, a light n-doping phenomenon (positive ${\Delta}n$ above $10^{10}cm^{-2}$ and negative ${\Delta}p$ below $-1.1{\times}10^{10}cm^{-2}$) occurs in the TMD devices doped by Co-DNA with $Tb^{3+}$ or $Er^{3+}$ ions. A significant (factor of ~5) increase in field-effect mobility is also observed on the $MoS_2$ and $WSe_2$ devices, which are, respectively, doped by $Tb^{3+}$-based Co-DNA (n-doping) and $Gd^{3+}$-based Co-DNA (p-doping), due to the reduction of effective electron and hole barrier heights after the doping. In terms of optoelectronic device performance (photoresponsivity and detectivity), the $Tb^{3+}$ or $Er^{3+}$-Co-DNA (n-doping) and the $Eu^{3+}$ or $Gd^{3+}$-Co-DNA (p-doping) improve the $MoS_2$ and $WSe_2$ photodetectors, respectively.