• The Journal of Korea Institute of Information, Electronics, and Communication Technology
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• v.1 no.1
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• pp.79-84
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• 2008

Proposed EEFL inverter design method with Dimming control to use microprocessor. Reduce power loss using Energy Recovery method, and design inverter control program that use RS-232 communication. Also, low temperature driving time shortened 50% that use duty variable control.

• Proceedings of the KIPE Conference
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• 1999.07a
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• pp.118-121
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• 1999

In this pager, we studies IGBT VVVF inverter for 1C4M propulsion system of railway traction. This inverter is consisted in inverter stack, DB unit, and control unit. To prove performance of inverter carry out combine test. This test verifies that performance of inverter is excellent.

• Proceedings of the KSR Conference
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• 2005.05a
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• pp.836-842
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• 2005

This paper presents a power supply of railway signal system using a Z-source inverter. The Z-source inverter overcomes the conceptual and theoretical barriers and limitations of the tradition voltage-source inverter and current-source inverter and provides novel power conversion concept. The Z-source inverter is a Buck-Boost inverter that has a wide range of obtainable voltage.

• The Transactions of the Korean Institute of Electrical Engineers B
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• v.48 no.1
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• pp.34-41
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• 1999

A three-level ZCT(Zero Current Transition) IGBT inverter is presented for high power IGBT inverters. The concept of ZCT for the conventional boost converter is extended to the three-level inverter. Moreover, in order to improve the reliability of inverter, midpoint charge balance problem of the three-level inverter is analyzed with respect 150kw, 20kHz prototype are presented to verify the principle of ZCT Operation.

• The Transactions of the Korean Institute of Electrical Engineers
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• v.43 no.6
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• pp.927-935
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• 1994

Detailed analysis of the commutation circuit of the proposed wide-frequency current source inverter is given. In this inverter a spike-limit circuit and a precommutation circuit are used. The spike-limit circuit is intended to limit spike voltage which is arising during commutation time in a current source inverter, and the precommutation circuit to reuse the energy which flows from main inverter to spike-limit circuit during commutation time to aid commutation. Thus voltage stress of main thyristor is minimized. Since this inverter can be made up of thyristors for phase control, it has some advantage in high voltage and high power application.

• Journal of Power Electronics
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• v.13 no.2
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• pp.223-231
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• 2013

A modular three-phase multilevel inverter especially suitable for electrical drive applications has been previously presented. This topology is based on series connection of power cells in which each cell comprised of two inverter legs in series. In this paper, in order to generate the maximum number of voltage levels with reduced number of switches, three algorithms are proposed for determination of the magnitudes of dc voltage sources. In addition, a new hybrid multilevel inverter is proposed that is composed of series connection of the previously presented multilevel inverter and some H-bridges. The proposed topology has been compared with some other presented multilevel inverters. The performance of the proposed multilevel inverter has been verified by simulation and experimental results of a single-phase 39-level multilevel inverter.

• Proceedings of the KIEE Conference
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• 1990.11a
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• pp.291-294
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• 1990

Fuel cell system needs DC-AC conversion inverter system because its output is DC. And the inverter system can be operated not only in stand-alone load but also in interactive mode in interactive mode, it is necessary to control active-reactive power of inverter and to synchronize inverter output voltage to power line voltage. In this paper, a 12 phase multiple VSI type GTO inverter system for fuel cell is described. Synchronization between power line voltage phase and inverter output voltage phase, and reduction of harmonics in the output voltage phase are the purpose of this inverter system. This control algorithm for the system is realized by the software method utilizing 8031AH 8bit Microprocessor.

• Journal of the Korean Institute of Illuminating and Electrical Installation Engineers
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• v.25 no.4
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• pp.124-134
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• 2011

A new dead time compensation scheme that can exactly estimate the dead time and inverter nonlinearity under parameter variations is proposed for a PWM inverter-fed PMSM drive. The proposed scheme uses the fact that the sixth harmonic component in total disturbance estimated under the presence of various uncertainties is mainly caused by the dead time and inverter nonlinearity. The total disturbance due to the parameter variations as well as the dead time and inverter nonlinearity is estimated by the adaptive scheme. The sixth harmonic component is extracted from this total disturbance through harmonic analysis. The obtained sixth harmonic is processed by the PI controller to estimate the disturbance caused by the dead time and inverter nonlinearity in the stationary reference frame. The effectiveness of the proposed scheme is verified. Without requiring an additional hardware, the proposed scheme can effectively compensate the dead time and inverter nonlinearity even under the parameter variations.

• Journal of Power Electronics
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• v.9 no.5
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• pp.726-735
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• 2009

This paper presents a Bidirectional High-Frequency Link (BHFL) inverter that utilizes the Deadbeat controller. The main features of this topology are the reduced size of the inverter and fewer power switches. On the secondary side of the transformer, the active rectifier employs only two power switches, thus reducing switching losses. Using this configuration, the inverter is capable of carrying a bidirectional power flow. The inverter is controlled by a Deadbeat controller, which consists of the inner current loop, outer voltage loop and a feedforward controller. Additional disturbance decoupling networks are employed to improve the system's robustness towards load variations. A 1-kVA prototype inverter has been constructed and the Deadbeat control algorithm is experimentally verified. The experimental results show that the inverter has high efficiency (91%) with low steady state output voltage total harmonics distortion (1.5%).

• Journal of Power Electronics
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• v.16 no.4
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• pp.1504-1512
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• 2016

This paper presents a new single-phase asymmetrical cascaded multilevel DC-link inverter. The proposed inverter comprises two stages. The main stage of the inverter consists of multiple similar cells, each of which is a half-bridge inverter consisting of two switches and a single DC source. All cells are connected in a cascaded manner with a fixed neutral point. The DC source values are not made equal to increase the performance of the inverter. The second circuit is a folded cascaded H-bridge circuit operating at a line frequency. One of the main advantages of this proposed topology is that it is a modular type and can thus be extended to high stages without changing the configuration of the main stage circuit. Two control schemes, namely, low switching with selective harmonic elimination and sinusoidal pulse width modulation, are employed to validate the proposed topology. The detailed approach of each control scheme and switching pulses are discussed in detail. A 150W prototype of the proposed system is implemented in the laboratory to verify the validity of the proposed topology.