• Journal of Broadcast Engineering
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• v.8 no.3
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• pp.228-237
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• 2003

Eureka-147 DAB(Digital Audio Broadcasting) system on which DMB(Digital Multimedia Broadcasting) system is based, was designed for the requirements of CD qualify audio with ${10}^{-4}$ bit error rate. Audio program may be primary service in DAB system, but multimedia program can be primary service in DMB system. Therefore, the bit error rate required must be below ${10}^{-7}$∼${10}^{-8}$ to transmit multimedia data via DMB channel. In order to meet the requirements and keep backward compatibility of DAB system we propose an outer channel coding scheme using Reed-Solomon coding and convolutional interleaving. This paper shows the simulation results for DMB channel performance based on mobile channel model. Also, it describes the needs and the effects of the outer channel coding.

• Journal of the Institute of Electronics and Information Engineers
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• v.50 no.7
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• pp.140-148
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• 2013

This paper presents a iterative Bose-Chaudhuri-hocquenghem (i-BCH) code and its high-speed decoder architecture for 100 Gb/s optical communications. The proposed architecture features a very high data processing rate as well as excellent error correction capability. The proposed 6-iteration i-BCH code structure with interleaving method allows the decoder to achieve 9.34 dB net coding gain performance at $10^{-15}$ decoder output bit error rate to compensate for serious transmission quality degradation. The proposed high-speed i-BCH decoder architecture is synthesized using a 90-nm CMOS technology. It can operate at a clock frequency of 430 MHz and achieve a data processing rate of 100 Gb/s. Thus, it has potential applications in next generation forward error correction (FEC) schemes for 100 Gb/s optical communications.

• Journal of Power Electronics
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• v.10 no.1
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• pp.9-13
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• 2010

This paper proposes an input-series-output-parallel connected ZVS full bridge converter with interleaved control for photovoltaic power conditioning systems (PV PCS). The input-series connection enables a fully modular power-system architecture, where low voltage and standard power modules can be connected in any combination at the input and/or at the output, to realize any given specifications. Further, the input-series connection enables the use of low-voltage MOSFETs that are optimized for a very low RDSON, thus, resulting in lower conduction losses. The system costs decrease due to the reduced current, and the volumes of the output filters due to the interleaving technique. A topology for a photovoltaic (PV) dc/dc converter that can dramatically reduce the power rating and increase the efficiency of a PV system by analyzing the PV module characteristics is proposed. The control scheme, consisting of an output voltage loop, a current loop and input voltage balancing loops, is proposed to achieve input voltage sharing and output current sharing. The total PV system is implemented for a 10-kW PV power conditioning system (PCS). This system has a dc/dc converter with a 3.6-kW power rating. It is only one-third of the total PV PCS power. A 3.6-kW prototype PV dc/dc converter is introduced to experimentally verify the proposed topology. In addition, experimental results show that the proposed topology exhibits good performance.

• Journal of IKEEE
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• v.2 no.2 s.3
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• pp.309-315
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• 1998

This paper describes an 8b 52 MHz CMOS subranging analog-to-digital converter (ADC) for Integrated Services Digital Network (ISDN) applications. The proposed ADC based on the improved time-interleaved architecture removes the holding time which is typically observed in the conventional double-channel subranging ADCs to increase throughput rate. Moreover, the ADC employs the interpolation technique in the back-end subranging ADCs far residue signal processing to minimize die area and power consumption. The fabricated and measured prototype ADC in a 0.8 um n-well double-poly double-metal CMOS process typically shows a 52 MHz sampling rate at a 5 V supply voltage with 230 mW, and a 40 MHz sampling rate at a 3 V power supply with 60 mW power consumption.

• The Journal of the Korea Contents Association
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• v.8 no.4
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• pp.63-70
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• 2008

This paper presents a method of PRI do-interleaving for LASER pulse signals. When the PRI of LASER pulse is periodically changed, the first deviation and the second deviation of TOA is used to calculate the PRI pattern of input LASER signals of receiver. If the standard deviation of the first difference of TOA is less than 5% of the average of the first difference of TOA, the PRI pattern of LASER signal is fixed or jittered type. If the standard deviation is larger than 5% of the average, those are triangular PRI patterns or sawtooth PRI patterns.

• Journal of the Institute of Electronics and Information Engineers
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• v.50 no.8
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• pp.21-27
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• 2013

In this paper, we propose a low-complexity Turbo coded BICM-ID (bit-interleaved coded modulation with iterative decoding) system. A Turbo code is a powerful error correcting code with a BER (bit error rate) performance very close to the Shannon limit. In order to increase spectral efficiency of the Turbo code, a coded modulation combining Turbo code with high order modulation is used. The BER performance of Turbo-BICM can be improved by Turbo-BICM-ID using iterative demodulation and decoding algorithm. However, compared with Turbo-BICM, the decoding complexity of Turbo-BICM-ID is increased by exchanging information between decoder and demodulator. To reduce the decoding complexity of Turbo-BICM-ID, we propose a low-complexity Turbo-BICM-ID system. When compared with conventional Turbo-BICM-ID, the proposed scheme not only show similar BER performance but also reduce the decoding complexity.

• Journal of the Institute of Electronics Engineers of Korea SD
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• v.42 no.6 s.336
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• pp.39-48
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• 2005

This paper proposes a reconfigurable coprocessor for communication systems, which can perform high speed computations and various functions. The proposed reconfigurable coprocessor can easily implement communication operations, such as scrambling, interleaving, convolutional encoding, Viterbi decoding, FFT, etc. The proposed architecture has been modeled by VHDL and synthesized using the SEC 0.18$\mu$m standard cell library. The gate count is about 35,000 gates and the critical path is 3.84ns. The proposed coprocessor can reduced about $33\%$ for FFT operations and complex MAC, $37\%$ for Viterbi operations, and $48\%\~84\%$ for scrambling and convolutional encoding for the IEEE 802.11a WLAN standard compared with existing DSPs. The proposed coprocessor shows Performance improvements compared with existing DSP chips for communication algorithms.

• Journal of the Korea Institute of Information and Communication Engineering
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• v.9 no.5
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• pp.1031-1038
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• 2005

In this paper, we propose real-time 3D image converting architecture by a unit of pixel for 2D/3D compatible PC and LCD of cellular phone with parallax burier, and implement a system for overall display operation after designing a circuit based on FPGA. After digitizing anolog image signal from PC, we recompose it to 3D image signal according to input image type. Since the architecture which rearranges 2D image to 3D depends on parallax burier, we use interleaving method which mixes pixels by a unit of R, G, and B cell. The propose architecture is designed into a circuit based on FPGA with high-speed memory access technique and use 4 SDRAMs for high performance data storing and processing. The implemented system consists of A/D converting system, FPGA system to formatting 2D signal to 3D, and LCD panel with parallax barrier, for 3D display.

• The Transactions of the Korean Institute of Power Electronics
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• v.13 no.6
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• pp.420-429
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• 2008

This paper describes design procedure and control strategy of HDC(High side DC/DC Converter) and MCU(Motor Control Unit) for diesel hybrid electric vehicle. In designing HDC and MCU for HEV high power density and reliability is strongly needed to meet the demand of automotive industry. In order to achieve the high performance of a controller, MPC5554 based control board is developed. An optimized film capacitor and inductor are also developed for high efficiency driving. Skim 63 IGBT module of SEMIKRON for automotive is used for power switching device. The most efficient cooling model for optimal size and reliability were verified by simulation. These procedures are verified by bench or driving test and the results are present in this paper.

• The Journal of Korean Institute of Communications and Information Sciences
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• v.36 no.9C
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• pp.537-545
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• 2011

This paper analyzed performance of three dimensional turbo code and turbo ${\Phi}$ codes proposed in the next generation DVB-RCS systems. In the view of turbo ${\Phi}$ codes, we proposed the optimal permutation and puncturing patterns for triple binary input data. We also proposed optimal post-encoder types and interleaving algorithm for three dimensional turbo codes. Based on optimal parameters, we simulated both turbo codes, and we confirmed that the performance of turbo ${\Phi}$ codes are better than that of three dimensional turbo codes. However, the complexity of turbo ${\Phi}$ is more complex than that of three dimensional turbo codes by 18%.