• Title/Summary/Keyword: interface-controlled mechanism

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A Study on the Manufacture of WC MMCs by In-situ Reaction Process(1);The Formation Mechanism of Interfacial Reaction Layer in Cast-bonded Cast iron/W wire and Its Structure (기지내 반응법에 의한 WC 복합재료의 제조에 관한 연구(1);주조접합된 주철/텅스텐 와이어의 계면반응층 생성기구와 조직특성)

  • Park, Heung-Il;Kim, Chang-Up;Huh, Bo-Young;Lee, Sung-Youl;Kim, Chang-Gyu
    • Journal of Korea Foundry Society
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    • v.15 no.3
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    • pp.272-282
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    • 1995
  • Iron-based metal matrix composites have been recently investigated for the use of inexpensive abrasion resistance material. This paper carried out to investigate the in-situ reaction effects on the microstructural characteristics and the formation mechanism of tungsten carbides in a white cast iron matrix. The specimens of Fe-3.2%C-2.8%Si alloy cast-bonded with tungsten wire were cast in the metal mold and isothermally heat treated at $950^{\circ}C$ up to 48 hours. The typical microstructure of heat treated specimens showed the reaction layer of WC at the interface of tungsten wire and the carbon depletion zone between the WC layer and the matrix. During the formation of WC layer, if the carbon supply is insufficient due to the decarburization of matrix or the isolation of matrix by cast-bonded W wires, the reaction layer develops coarse hexagonal crystalline WC. From the microstructural investigation, it was found that the volume of WC layer and the carbon depletion zone increased linearly with the isothermal heat treating time. This results supported that the formation rate of WC in the white cast iron matrix is controlled by the interfacial reaction with a constant reaction rate.

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Characterization of the Schottky Barrier Height of the Pt/HfO2/p-type Si MIS Capacitor by Internal Photoemission Spectroscopy (내부 광전자방출 분광법을 이용한 Pt/HfO2/p-Si Metal-Insulator-Semiconductor 커패시터의 쇼트키 배리어 분석)

  • Lee, Sang Yeon;Seo, Hyungtak
    • Korean Journal of Materials Research
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    • v.27 no.1
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    • pp.48-52
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    • 2017
  • In this study, we used I-V spectroscopy, photoconductivity (PC) yield and internal photoemission (IPE) yield using IPE spectroscopy to characterize the Schottky barrier heights (SBH) at insulator-semiconductor interfaces of Pt/$HfO_2$/p-type Si metal-insulator-semiconductor (MIS) capacitors. The leakage current characteristics of the MIS capacitor were analyzed according to the J-V and C-V curves. The leakage current behavior of the capacitors, which depends on the applied electric field, can be described using the Poole-Frenkel (P-F) emission, trap assisted tunneling (TAT), and direct tunneling (DT) models. The leakage current transport mechanism is controlled by the trap level energy depth of $HfO_2$. In order to further study the SBH and the electronic tunneling mechanism, the internal photoemission (IPE) yield was measured and analyzed. We obtained the SBH values of the Pt/$HfO_2$/p-type Si for use in Fowler plots in the square and cubic root IPE yield spectra curves. At the Pt/$HfO_2$/p-type Si interface, the SBH difference, which depends on the electrical potential, is related to (1) the work function (WF) difference and between the Pt and p-type Si and (2) the sub-gap defect state features (density and energy) in the given dielectric.

Crystallopraphic Growth Orientation of Polycrystalline HSG Silicon Film (반구형 다결정 실리콘 박막의 결정학적 성장방위)

  • Sin, Dong-Won;Park, Chan-Ro;Park, Chan-Gyeong;Kim, Jong-Cheol
    • Korean Journal of Materials Research
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    • v.4 no.7
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    • pp.750-758
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    • 1994
  • The purpose of present study is to find out the formation mechanism of hemi-spherical grained(HSG) polysilicon film. Silicon film was deposited using LPCVD. Polycrystalline silicon film was deposited at $575^{\circ}C$ contained crystalline HSG in the amorphous matrix phase. The crystalline HSG can be categorized into two grains : lower grains and upper grains. Lower grains are located at interface between silicon dioxide and silicon film, and upper grains are located at surface. The growth orientations of HSG were identified as (311) or (111) directions for lower grains and perferentially (110) direction for upper grains. This difference of growth orientations seems to be caused by the difference of formation mechanisms. That is, lower grain is formed by soild phase crystallization, on the other hand, upper grain is formed by surface diffusion of silicon atoms. It was thus, proposed that the formation of practical HSG polysilicon film is mainly controlled by surface diffusion of silicon atoms.

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Characteristics of Self assembled Monolayer as $Ta_2O_5$ Dielectric Interface for Polymer TFTs (중합 박막 트랜지스터를 위한 $Ta_2O_5$ 유전체 접합의 자기조립 단분자막의 특성)

  • Choi, Kwang-Nam;Kwak, Sung-Kwan;Chung, Kwan-Soo;Kim, Dong-Sik
    • 전자공학회논문지 IE
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    • v.43 no.1
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    • pp.1-4
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    • 2006
  • The characteristics of polymeric thin-film transistors(TFTs) can be controlled by chemically modifying the surface of the gate dielectric prior to the organic semiconductor. The chemical treatment consists of derivative the tantalum pentoxide($Ta_2O_5$) surface with organic materials to form self-assembled monolayer(SAM). The deposition of an octadecyl-trichlorosilane(OTS), hexamethy-ldisilazone(HMDS), aminopropyltreithoxysilane(ATS) SAM leads to a mobility of $0.01\sim0.06cm2/V{\cdot}s$ in a poly-3-hexylthiophene(P3HT) conjugated polymer. The mobility enhancement mechanism is likely to involve molecular interactions between the polymer and SAM. These result can be used for polymer TFT's dielectric material.

A study on the electrical characteristics of CdZnS/CdTe heterojunction (CdZnS/CdTe 이종접합의 전기적 특성에 관한 연구)

  • Lee, Jae-Hyeong
    • Journal of the Korea Institute of Information and Communication Engineering
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    • v.14 no.7
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    • pp.1647-1652
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    • 2010
  • A CdS film has been used as a window layer in CdTe and Cu(In,Ga)$Se_2$ thin films solar cell. Partial substitution of Zn for Cd increases the photocurrent and the open-circuit voltage by providing a match in the electron affinities of the two materials and the higher band gap. In this paper, CdZnS/CdTe and CdS/CdTe heterojunctions were fabricated and the electrical characteristics were investigated. Current-voltage-temperature measurements showed that the current transport for CdS/CdTe heterojunction was controlled by both tunneling and interface recombination. However, CdZnS/CdTe heterojunction displayed different current transport mechanism with the operating temperature. For above room temperature, the current transport of device was generation/recombination in the depletion region and was the leakage current and/or tunneling in the range below room temperature.

Design and Development of PCI-based 1553B Communication Software for Next Generation LEO On-Board Computer (차세대 저궤도 위성의 PCI 기반의 1553B 통신 소프트웨어 설계)

  • Choi, Jong-Wook;Jeong, Jae-Yeop;Yoo, Bum-Soo
    • Journal of Satellite, Information and Communications
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    • v.11 no.3
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    • pp.65-71
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    • 2016
  • Currently developing the OBC of the next-generation LEO satellite by Korea Aerospace Research Institute adopts the LEON2-FT/AT697F processor to achieve high performance. And various communication devices such as SpaceWire, MIL-STD-1553B, DMAUART and CAN Master are integrated to the separated standard communication FPGAs within the OBC, where they can be controlled by the processor and flight software (FSW) through PCI interface. The Actel 1553BRM IP core is used for the 1553B in the next-generation LEO OBC and the B1553BRM wrapper from Aeroflex Gaisler is used for connecting it to the AMBA bus in FPGA. This paper presents the design and development of PCI-based 1553B communication software, and describes the handling mechanism of 1553B operation in FSW task level. Also it shows the test results on real-hardware and simulator.

Electrical/Dielectric Characterization of 2-Dimenisonal Electron Gas Layers Formed between LaAlO3 and SrTiO3

  • Park, Chan-Rok;Kwon, Kyeong-Woo;Do, Woo-ri;Park, Da-Hee;Baek, Senug-Hyub;Kim, Jin Sang;Hwang, in-Ha
    • Proceedings of the Korean Vacuum Society Conference
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    • 2014.02a
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    • pp.366.2-366.2
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    • 2014
  • Impedance spectroscopy allows for simultaneous characterization of interface-controlled materials and/or devices in terms of electrical and dielectric aspects. Recently, there have tremendous interests in 2-dimensional electron gas layers (2DEGs) involving $LaAlO_3$ and $SrTiO_3$ whose features incorporates extremely high mobility and carrier concentrations along with metallic responses unlike the constituents, $LaAlO_3$ and $SrTiO_3$. Impedance spectroscopy offers the following unique features, such as simultaneous determination of conductivity and dielectric constants, identification of electrical origins among bulk-, grain boundary-, and electrode-based responses. Impedance spectroscopy was applied to the 2DEG $LaAlO_3/SrTiO_3$ system, in order to extract the electrical and dielectric information operating in the 2DEG system. The unique responses of the 2DEG system are investigated in terms of temperature and device structures. The underlying mechanism of the 2DEG system is proposed with the aim to optimizing the high-mobility 2DEG responses and to expedite the associated devices towards the high-density integrated chips.

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The Interface Reaction Between Molten Converter Slag and $C_3A(3CaO{\cdot}Al_2O_3)$ Pellet (용융전로(熔融轉爐)슬래그와 $C_3A(3CaO{\cdot}Al_2O_3)$ 펠렛사이의 계면반응(界面反應))

  • Kim, Young-Hwan;Ko, In-Yong
    • Resources Recycling
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    • v.14 no.5 s.67
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    • pp.13-17
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    • 2005
  • As a basic study for recycling molten converter slag as an ordinary portland cement (OPC) by a conversion process, the reaction mechanism and the rate of the formation of $C_4AF$ which is one of the main components of OPC were investigated. The converter slag whose basicity was controlled by adding reagent grade $SiO_2$ was melted and hold for 30 minutes in MgO crucible at $1300^{\circ}C{\sim}1350^{\circ}C$. Then, the sintered CaO pellet heated at the same temperature was dipped into the molten slag and hold for $10{\sim}30$minutes. After the reaction, the crucible was cooled in air and the specimen was cut off to the horizontal direction of the crucible. The dissolution rate of $C_3A$ pellet was measured by the change of radius of the sintered $C_3A$ pellet, and the formed phase of $C_4AF$ was observed by SEM/EDX. As a result, the dissolution rate of $C_3A$ pellet into molten slag was increased from $0.75{\times}10^{-4}(cm/sec)$ at $1300^{\circ}C$ to $1.67{\times}10^{-4}(cm/sec)$ at $1350^{\circ}C$, and the mixed layer of $C_4AF$ and $C_{12}A_7$ was found between slag and $C_3A$ pellet.

Kinetic Studies on Cooking of Rice of Various Polishing Degrees (도정도별 쌀의 취반에 대한 역학적 연구)

  • Cheigh, Hong-Sik;Kim, Sung-Kon;Pyun, Yu-Ryang;Kwon, Tai-Wan
    • Korean Journal of Food Science and Technology
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    • v.10 no.1
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    • pp.52-56
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    • 1978
  • The mechanism of cooking rice was investigated using a japonica type rice variety, Akibare, of 50%, 70% and 90% polishing degrees. The hardness of rice cooked at various cooking temperatures ($90^{\circ}-120^{\circ}C$) was measured with a Texturometer. The cooking rate followed the equation of a first-order reaction. The reaction rate constants were in the increasing order of 50%, 70% and 90% polished rice. The temperature coefficient of the reaction rate constant at cooking temperatures of ($90^{\circ}-100^{\circ}C$) was about 2 in all rice samples. The activation energies of cooking at temperatures below $100^{\circ}C$ and above $100^{\circ}C$ were about 17,000 and 9,000 cal/mole, respectively. The polishing degrees and water soaking time of rice did not affect the activation energy of cooking; however, the lower polishing degrees and shorter soaking increased the cooking time The experimental results suggested that the cooking process of rice comprises two mechanisms: At temperatures below $100^{\circ}C$ the cooking rate is controlled by the reaction rate of rice constituents with water, and at temperatures above $100^{\circ}C$, it is controlled by the rate of diffusion of water through the cooked portion (or layer) toward the interface of uncooked core in which the reaction is occurring.

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Fault Tolerance for IEEE 1588 Based on Network Bonding (네트워크 본딩 기술을 기반한 IEEE 1588의 고장 허용 기술 연구)

  • Altaha, Mustafa;Rhee, Jong Myung
    • The Journal of Korea Institute of Information, Electronics, and Communication Technology
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    • v.11 no.4
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    • pp.331-339
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    • 2018
  • The IEEE 1588, commonly known as a precision time protocol (PTP), is a standard for precise clock synchronization that maintains networked measurements and control systems. The best master clock (BMC) algorithm is currently used to establish the master-slave hierarchy for PTP. The BMC allows a slave clock to automatically take over the duties of the master when the slave is disconnected due to a link failure and loses its synchronization; the slave clock depends on a timer to compensate for the failure of the master. However, the BMC algorithm does not provide a fast recovery mechanism in the case of a master failure. In this paper, we propose a technique that combines the IEEE 1588 with network bonding to provide a faster recovery mechanism in the case of a master failure. This technique is implemented by utilizing a pre-existing library PTP daemon (Ptpd) in Linux system, with a specific profile of the IEEE 1588 and it's controlled through bonding modes. Network bonding is a process of combining or joining two or more network interfaces together into a single interface. Network bonding offers performance improvements and redundancy. If one link fails, the other link will work immediately. It can be used in situations where fault tolerance, redundancy, or load balancing networks are needed. The results show combining IEEE 1588 with network bonding enables an incredible shorter recovery time than simply just relying on the IEEE 1588 recovery method alone.