• Journal of Sensor Science and Technology
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• v.31 no.4
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• pp.271-277
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• 2022

We analyzed the effects of the interface trap on the output characteristics of an inversion mode n-channel GaN Schottky barrier (SB)-MOSFET based on the N_it distribution using TCAD simulation. As interface trap number density (N_it) increased, the threshold voltage increased while the drain current density decreased. Under N_it=5.0×10¹⁰ cm^-2 condition, the threshold voltage was 3.2 V for V_DS=1 V, and the drain current density reduced to 2.4 mA/mm relative to the non-trap condition. Regardless of the N_it distribution type, there was an increase in the subthreshold swing (SS) following an increase in N_it. Under U-shaped N_it distribution, it was confirmed that the SS varied depending on the gate voltage. The interface fixed charge (Q_f) caused an shift in the threshold voltage and increased the off-state current collectively with the surface trap. In summary, GaN SB-MOSFET can be a building block for high power UV optoelectronic circuit provided the surface state is significantly reduced.

• Journal of Sensor Science and Technology
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• v.27 no.3
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• pp.150-155
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• 2018

Three different structures of GaN MOSFETs with trap distributions, trap levels, and densities were simulated, and its results were analyzed. Two of them are Schottky barrier MOSFETs(SB-MOSFETs): one with a p-type GaN body while the other is in the accumulation mode MOSFET with an undoped GaN body and regrown source/drain. The trap levels, distributions and densities were considered based on the measured or calculated properties. For the SB-MOSFET, the interface trap distribution affected the threshold voltage significantly, but had a relatively small influence on the subthreshold swing, while the bulk trap distribution affects the subthreshold swing more.

• JSTS:Journal of Semiconductor Technology and Science
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• v.15 no.5
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• pp.497-503
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• 2015

It is essential to acquire an accurate and simple technique for extracting the interface trap density ($D_{it}$) in order to characterize the normally-off gate-recessed AlGaN/GaN hetero field-effect transistors (HFETs) because they can undergo interface trap generation induced by the etch damage in each interfacial layer provoking the degradation of device performance as well as serious instability. Here, the frequency-dependent capacitance-voltage (C-V) method (FDCM) is proposed as a simple and fast technique for extracting $D_{it}$ and demonstrated in normally-off gate-recessed AlGaN/GaN HFETs. The FDCM is found to be not only simpler than the conductance method along with the same precision, but also much useful for a simple C-V model for AlGaN/GaN HFETs because it identifies frequency-independent and bias-dependent capacitance components.

• Proceedings of the Korean Institute of Electrical and Electronic Material Engineers Conference
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• 2007.11a
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• pp.157-158
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• 2007

Effects of post-metallization anneal (PMA) on interface trap characteristics of Si-$SiO_2$ are studied. The conventional PMA method utilizes forming gas anneal, where 10% hydrogen in nitrogen atmosphere is used. A new PMA method utilizes hydrogen rich PECVD- silicon nitride $(SiN_x)$ film as a hydrogen diffusion source and a out-diffusion blocking layer. It can be shown through charge pumping current measurement that the new PMA is indeed effective to decrease Si-$SiO_2$ interface trap density.

• JSTS:Journal of Semiconductor Technology and Science
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• v.12 no.3
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• pp.360-369
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• 2012

The causes of showing different subthreshold slopes (SS) in programmed and erased states for two different charge trap flash (CTF) memory devices, SONOS type flash memory with gate-all-around (GAA) structure and TANOS type NAND flash memory with planar structure were investigated. To analyze the difference in SSs, TCAD simulation and low-frequency noise (LFN) measurement were fulfilled. The device simulation was performed to compare SSs considering the gate electric field effect to the channel and to check the localized trapped charge distribution effect in nitride layer while the comparison of noise power spectrum was carried out to inspect the generation of interface traps ($N_{IT}$). When each cell in the measured two memory devices is erased, the normalized LFN power is increased by one order of magnitude, which is attributed to the generation of $N_{IT}$ originated by the movement of hydrogen species ($h^*$) from the interface. As a result, the SS is degraded for the GAA SONOS memory device when erased where the $N_{IT}$ generation is a prominent factor. However, the TANOS memory cell is relatively immune to the SS degradation effect induced by the generated $N_{IT}$.

• Proceedings of the Korean Institute of Electrical and Electronic Material Engineers Conference
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• 1999.11a
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• pp.453-456
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• 1999

The Si-SiO$_2$interface trap and nitride bulk trap distribution of SONOSFET(polysilicon-oxide-nitride-oxide-semiconductor)NVSM(nonvolatile semiconductor memory) cell were investigated by single charge pumping method. The used device was fabricated by 0.35 7m standard logic fabrication including the ONO cell process. This ONO dielectric thickness is tunnel oxide 24 $\AA$, nitride 74 $\AA$, blocking oxide 25 $\AA$, respectively. Keeping the pulse base level in accumulation and pulsing the surface into inversion with increasing amplitudes, the charge pumping current flow from the single junction. Using the obtained I$_{cp}$-V$_{h}$ curve, the local V$_{t}$ distribution, doping concentration, lateral interface trap distribution and lateral memory trap distribution were extracted. The maximum N$_{it}$($\chi$) of 1.62$\times$10$^{19}$ /cm$^2$were determined.mined.d.

• Journal of the Institute of Electronics Engineers of Korea SD
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• v.41 no.8
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• pp.1-8
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• 2004

Experimental results are presented for gate oxide degradation, such as SILC and soft breakdown, and its effect on device parameters under negative and positive bias stress conditions using n-MOSFET's with 3 nm gate oxide. The degradation mechanisms are highly dependent on stress conditions. For negative gate voltage, both interface and oxide bulk traps are found to dominate the reliability of gate oxide. However, for positive gate voltage, the degradation becomes dominated mainly by interface trap. It was also found the trap generation in the gate oxide film is related to the breakage of Si-H bonds through the deuterium anneal and additional hydrogen anneal experiments. Statistical parameter variations as well as the “OFF” leakage current depend on both electron- and hole-trapping. Our results therefore show that Si or O bond breakage by tunneling electron and hole can be another origin of the investigated gate oxide degradation. This plausible physical explanation is based on both Anode-Hole Injection and Hydrogen-Released model.

• JSTS:Journal of Semiconductor Technology and Science
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• v.15 no.1
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• pp.16-21
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• 2015

In this study, the effects of forming gas post metallization annealing (PMA) on recessed AlGaN/GaN-on-Si MOSHFET were investigated. The device employed an ICPCVD $SiO_2$ film as a gate oxide layer on which a Ni/Au gate was evaporated. The PMA process was carried out at $350^{\circ}C$ in forming gas ambient. It was found that the device instability was improved with significant reduction in interface trap density by forming gas PMA.

• JSTS:Journal of Semiconductor Technology and Science
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• v.12 no.4
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• pp.449-457
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• 2012

The program/erase (P/E) cyclic endurances including bias temperature instability (BTI) behaviors of Metal-$Al_2O_3$-Nitride-Oxide-Semiconductor (MANOS) memories are investigated in comparison with those of Semiconductor-Oxide-Nitride-Oxide-Semiconductor (SONOS) memories. In terms of BTI behaviors, the SONOS power-law exponent n is ~0.3 independent of the P/E cycle and the temperature in the case of programmed cell, and 0.36~0.66 sensitive to the temperature in case of erased cell. Physical mechanisms are observed with thermally activated $h^*$ diffusion-induced Si/$SiO_2$ interface trap ($N_{IT}$) curing and Poole-Frenkel emission of holes trapped in border trap in the bottom oxide ($N_{OT}$). In terms of the BTI behavior in MANOS memory cells, the power-law exponent is n=0.4~0.9 in the programmed cell and n=0.65~1.2 in the erased cell, which means that the power law is strong function of the number of P/E cycles, not of the temperature. Related mechanism is can be explained by the competition between the cycle-induced degradation of P/E efficiency and the temperature-controlled $h^*$ diffusion followed by $N_{IT}$ passivation.

• Proceedings of the Korean Institute of Electrical and Electronic Material Engineers Conference
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• 2004.07a
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• pp.17-19
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• 2004

The electrical properties of gate oxides grown in two different processes, which are in 10% nitrous oxide($N_2O$) and in dry oxygen, have been experimentally investigated and compared. It has been observed that the $SiC-SiO_2$ interface-trap density(Dit) measured in nitrided gate oxide has been tremendously reduced, compared to the density obtained from gate oxide grown in dry oxygen. The beneficial effects of nitridation on gate oxides also have been demonstrated in the values of total near interface-trap density and of forward-bias breakdown field. The reasons of these improvements have been explained.