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http://dx.doi.org/10.5573/JSTS.2012.12.4.449

Comparative investigation of endurance and bias temperature instability characteristics in metal-Al2O3-nitride-oxide-semiconductor (MANOS) and semiconductor-oxide-nitride-oxide-semiconductor (SONOS) charge trap flash memory  

Kim, Dae Hwan (School of Electrical Engineering , Kookmin University)
Park, Sungwook (School of Electrical Engineering , Kookmin University)
Seo, Yujeong (Department of Electronics Engineering, Korea University)
Kim, Tae Geun (Department of Electronics Engineering, Korea University)
Kim, Dong Myong (School of Electrical Engineering , Kookmin University)
Cho, Il Hwan (Department of Electronic Engineering , Myongji University)
Publication Information
JSTS:Journal of Semiconductor Technology and Science / v.12, no.4, 2012 , pp. 449-457 More about this Journal
Abstract
The program/erase (P/E) cyclic endurances including bias temperature instability (BTI) behaviors of Metal-$Al_2O_3$-Nitride-Oxide-Semiconductor (MANOS) memories are investigated in comparison with those of Semiconductor-Oxide-Nitride-Oxide-Semiconductor (SONOS) memories. In terms of BTI behaviors, the SONOS power-law exponent n is ~0.3 independent of the P/E cycle and the temperature in the case of programmed cell, and 0.36~0.66 sensitive to the temperature in case of erased cell. Physical mechanisms are observed with thermally activated $h^*$ diffusion-induced Si/$SiO_2$ interface trap ($N_{IT}$) curing and Poole-Frenkel emission of holes trapped in border trap in the bottom oxide ($N_{OT}$). In terms of the BTI behavior in MANOS memory cells, the power-law exponent is n=0.4~0.9 in the programmed cell and n=0.65~1.2 in the erased cell, which means that the power law is strong function of the number of P/E cycles, not of the temperature. Related mechanism is can be explained by the competition between the cycle-induced degradation of P/E efficiency and the temperature-controlled $h^*$ diffusion followed by $N_{IT}$ passivation.
Keywords
MANOS memory; SONOS memory; bias temperature instability; interface trap;
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