Kim, Dae Hwan
(School of Electrical Engineering , Kookmin University)
Park, Sungwook (School of Electrical Engineering , Kookmin University) Seo, Yujeong (Department of Electronics Engineering, Korea University) Kim, Tae Geun (Department of Electronics Engineering, Korea University) Kim, Dong Myong (School of Electrical Engineering , Kookmin University) Cho, Il Hwan (Department of Electronic Engineering , Myongji University) |
1 | W. B. Shim, S. Cho, J. H. Lee, D. H. Li, D. -H. Kim, G. S. Lee, Y. Kim, S. H Park, W. Kim, J. C. Choi, and B. -G. Park, "Stacked Gate Twin-Bit(SGTB) SONOS Memory Device for High-Density Flash Memory," IEEE Trans. Nanotechnology, vol. 11, no. 2, pp. 307-313, Mar. 2012. DOI ScienceOn |
2 | M. L. French, C. -Y. Chen, H. Sathianathan, and M. H. White, "Design and Scaling of a SONOS Multidielectric Device for Nonvolatile Memory Applications," IEEE Trans. Components Packaging and Manufacturing Technology Part A, vol. 17, no. 3, pp. 390-397, Sep. 1994. DOI |
3 | C. -H. Lee, K. -C. Park, and K. Kim, "Chargetrapping memory cell of dielectric with TaN metal gate for suppressing backward-tunneling effect," Appl. Phys. Lett., vol. 87, no. 7, p. 073510, Aug. 2005. DOI ScienceOn |
4 | J. Willer, C. Ludwiq, J. Deppe, C. Kleint, S. Riedel, J. -U. Sachse, M. Krause, R. Mikalo, E. S. Kamienski, S. Parascandola, T. Mikolajick, J. -M. Fischer, M. Isler, K.-H. Kuesters, I. Bloom, A. Shapir, E. Lusky, and B. Eitan, "110 nm NROM technology for code and data flash products," in VLSI Symp. Tech. Dig., pp. 76-77, Jun. 2004. |
5 | Y. Igura, H. Matsuoka, and E. Takeda, "New device degradation due to "cold" carriers created by band-to-band tunneling," IEEE Electron Device Lett., vol. 10, no. 5, pp. 227-229, May 1989. DOI ScienceOn |
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7 | S. Haddad, C. Chang, A. Wang, J. Bustillo, J. Lien, T. Montalvo, and M. Van Buskirk, "An investigation of erase-mode dependent hole trapping in flash EEPROM memory cell," IEEE Electron Device Lett., vol. 11, no. 11, pp. 514-516, Nov. 1990. DOI ScienceOn |
8 | D. K. Schroder, Semiconductor Material and Device Characterization, 3rd ed., Wiley, New York, 2006. |
9 | X. Wang and D.-L. Kwong, "A novel high-k SONOS memory using TaN/Al2O3/Ta2O5/HfO2/Si structure for fast speed and long retention operation," IEEE Trans. Electron Devices, vol. 53, no. 1, pp. 78-82, Jan. 2006. DOI ScienceOn |
10 | T. -H. Hsu, H. -T. Lue, E. -K. Lai, J. -Y. Hsieh, S. -Y. Wang, L. -W. Yang, Y. -C. King, T. Yang, K. -C. Chen, K. -Y. Hsieh, R. Liu, and C. -Y. Lu, "A high-speed BE-SONOS NAND flash utilizing the field-enhancement effect of FinFET," in IEDM Tech. Dig., pp. 913-916, Dec. 2007. |
11 | A. Furnémont, M. Rosmeulen, A. Cacciato, L. Breuil, K. De Meyer, H. Maes, and J. Van Houdt, "Physical understanding of SANOS disturbs and VARIOT engineered barrier as a solution," in Proc. NVSM Workshop, pp. 94-95, Aug. 2007. |
12 | S. H. Seo, G. -C. Kang, K. S. Roh, K. Y. Kim, S. Lee, K. -J. Song, C. M. Choi, S. R. Park, K. Jeon, J. -H. Park, B. -G. Park, J. D. Lee, D. M. Kim, and D. H. Kim, "Dynamic bias temperature instabilitylike behaviors under Fowler-Nordheim program/erase stress in nanoscale silicon-oxide-nitrideoxide-silicon memories," Appl. Phys. Lett., vol. 92, no. 13 , p. 133508, Apr. 2008. DOI ScienceOn |
13 | S. -K Sung, I. -H. Park, C. J. Lee, Y. K. Lee, J. D. Lee, B. -G. Park, S. D. Chae, and C. W. Kim, "Fabrication and program/erase characteristics of 30-nm SONOS nonvolatile memory devices," IEEE Trans. Nanotechnology, vol. 2, no. 4, pp. 258-264, Dec. 2003. DOI ScienceOn |
14 | J. -H. Yi, H. Shin, Y.-J. Park, and H. S. Min, "Polarity-dependent device degradation in SONOS transistors due to gate conduction under nonvolatile memory operations," IEEE Trans. Device and Materials Reliability, vol. 6, no. 2, pp. 334-342, Jun. 2006. DOI ScienceOn |
15 | B. Verzi, and P. Aum, "Automated gated diode measurements for device characterization," in Proc. IEEE Int. Conf. Microelec. Test Struc., pp. 141-146, Mar. 1994. |
16 | S. Mahapatra, M. A. Alam, P. B. Kumar, T. R. Dalei, D. Varghese, and D. Saha, "Negative bias temperature instability in CMOS devices," Microelectron. Eng., vol. 80, pp. 114-121, Jun. 2005. DOI ScienceOn |
17 | S. Mahapatra, D. Saha, D. Varghese, and P. B. Kumar, "On the Generation and recovery of interface traps in MOSFETs subjected to NBTI, FN, and HCI stress," IEEE Trans. Electron Devices, vol. 53, no. 7, pp. 1583-1592, Jul. 2006. DOI ScienceOn |
18 | D. Saha, D. Varghese, and S. Mahapatra, "Role of anode hole injection and valence band hole tunneling on interface trap generation during hot carrier injection stress," IEEE Electron Device Lett., vol. 27, no. 7, pp. 585-587, Jul. 2006. DOI ScienceOn |
19 | D. Varghese, S. Mahapatra, and M. A. Alam, "Hole energy dependent interface trap generation in MOSFET Si/SiO2 interface," IEEE Electron Device Lett., vol. 26, no. 8, pp. 572-574, Aug. 2005. DOI ScienceOn |
20 | C. H. Chen, P. Y. Chiang, S. S. Chung, T. Chen, G. C. W. Chou, and C. H. Chu, "Understanding of the leakage components and its correlation to the oxide scaling on the SONOS cell endurance and retention," in VLSI Symp. Technol. Sys. Applic., pp. 1-2, Apr. 2006. |