• Journal of the Korean Institute of Telematics and Electronics A
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• v.32A no.6
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• pp.91-103
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• 1995

This paper presents the design of a performance-driven interconnect allocation algorithm. The algorithm is based on the idea that the clock period can be minimized by balancing the load for each of the communication paths following specific hardware modules. By performing load balancing for only the communication lines on ciritical paths, the proposed algorithm generates interconnection structures with minimum delays. This approach also shows run time efficiency. Experimental results confirm the effectiveness of the algorithm by constructing the interconnection structures such that the clock period can be minimized for several benchmark circuits available from the literature.

• The Journal of Society for e-Business Studies
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• v.7 no.1
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• pp.225-237
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• 2002

As the population of the Internet inneases, so does that of mobile Internet. Currently, the use area of mobile Internet is rather limited due to the low speed of transmission and lack of applications. However, it is evident that the speed will be improved and more applications will be developed. In this paper, we propose： i) to use WAP in SCM, ii) to interconnect WAP and XML/EDI system, iii) to interconnect WAP, XML/EDI, Legacy system in SCM. We implemented a prototype which can show the interconnection among WAP, XML/EDI, and Legacy system. We hope the concept could be used in real applications in the near future.

• JSTS:Journal of Semiconductor Technology and Science
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• v.13 no.6
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• pp.594-607
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• 2013

A new efficient analytical eye-diagram determination technique for coupled interconnect lines is presented. Two coupled lines are decoupled into isolated eigen modes; bit blocks for coupled lines, which are defined as a block of consecutive bits, are then represented with decoupled modes. The crosstalk effects within the bit blocks are taken into account. Thereby, the crucial input bit patterns for the worst case eye-diagram determination are modeled mathematically, including inter-symbol interference (ISI). The proposed technique shows excellent agreement with the SPICE-based simulation. Furthermore, it is very computation-time-efficient in the order of magnitude, compared with the SPICE simulation, which requires numerous pseudo-random bit sequence (PRBS) input signals.

• JSTS:Journal of Semiconductor Technology and Science
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• v.7 no.4
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• pp.260-266
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• 2007

Analytical compact form models for the signal transients and crosstalk noise of inductive-effect-prominent multi-coupled RLC lines are developed. Capacitive and inductive coupling effects are investigated and formulated in terms of the equivalent transmission line model and transmission line parameters for fundamental modes. The signal transients and crosstalk noise expressions of two coupled lines are derived by using a waveform approximation technique. It is shown that the models have excellent agreement with SPICE simulation.

• Korean Journal of Materials Research
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• v.17 no.7
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• pp.347-351
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• 2007

Vertical interconnect technology called 3D stacking has been a major focus of the next generation of IC industries. 3D stacked devices in the vertical dimension give several important advantages over conventional two-dimensional scaling. The most eminent advantage is its performance improvement. Vertical device stacking enhances a performance such as inter-die bandwidth improvements, RC delay mitigation and geometrical routing and placement advantages. At present memory stacking options are of great interest to many industries and research institutes. However, these options are more focused on a form factor reduction rather than the high performance improvements. In order to improve a stacked device performance significantly vertical interconnect technology with wafer level stacking needs to be much more progressed with reduction in inter-wafer pitch and increases in the number of stacked layers. Even though 3D wafer level stacking technology offers many opportunities both in the short term and long term, the full performance benefits of 3D wafer level stacking require technological developments beyond simply the wafer stacking technology itself.

• 한국신재생에너지학회:학술대회논문집
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• 2011.11a
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• pp.91.2-91.2
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• 2011

고체산화물 연료전지의 연결재의 필요한 물성으로는 공기극과 연료극을 차폐시켜줄 수 있는 고밀도와 구성 소재간의 전기적으로 연결될 수 있는 전기전도도 및 낮은 이온전도도. 산화극과 환원극에서 화학적 안정성과 타 구성 소재와의 열팽창 계수가 일치 등이 중요한 특성으로 필요하게 된다. 이를 위해 LaCrO3계 연결재가 주로 사용되어 왔다. 그러나 LCO계 연결제는 $1400^{\circ}C$ 이상의 높은 소결 온도와 이로 인한 Cr의 휘발로 인한 타 구성소재와의 반응 등으로 인해 저온소결의 필요성이 재기되고 있는 소재 이다. 본 연구에서는 LCO계 구성 소제에 소결 조제를 첨가하여 저온에서 결정성 및 소결거동, 전기적 특성을 평가하였다.

• The Transactions of the Korean Institute of Electrical Engineers D
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• v.49 no.11
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• pp.637-642
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• 2000

IEEE 1149.1 boundary scan architecture is used as a standard in board-level system testing. The simplicity of this architecture is an advantage in system testing, but at the same time, it it makes a limitation of applications. Because of several problems such as 3-state net conflicts, or ambiguity issues, interconnect testing for multi-drop multi-board systems is more difficult than that of single board systems. A new approach using IEEE 1149.1 boundary scan architecture for multi-drop multi-board systems is developed in this paper. Adding boundary scan cells on backplane bus lines, each board has a complete scan-chain for interconnect test. This new scan-path insertion method on backplane bus using limited 1149.1 test bus less area overhead and mord efficient than previous approaches.

• JSTS:Journal of Semiconductor Technology and Science
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• v.11 no.4
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• pp.318-328
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• 2011

Stage-level reconfigurable chip multiprocessor (CMP) aims to achieve highly reliable and fault tolerant computing by using interwoven pipeline stages and on-chip interconnect for communicating with each other. The existing crossbar-switch based stage-level reconfigurable CMPs offer high reliability at the cost of significant area/power overheads. These overheads make realizing large CMPs prohibitive due to the area and power consumed by heavy interconnection networks. On other hand, area/power-efficient architectures offer less reliability and inefficient stage-level resource utilization. In this paper, I propose a hierarchical multiplexing interconnection structure in lieu of crossbar interconnect to design area/power-efficient stage-level reconfigurable CMP. The proposed approach is able to keep the reliability offered by the crossbar-switch while reducing the area and power overheads. Experimental results show that the proposed approach reduces area by up to 21% and power by up to 32% when compared with the crossbar-switch based interconnection network.

• JSTS:Journal of Semiconductor Technology and Science
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• v.11 no.1
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• pp.15-22
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• 2011

Interconnect lines with inter-layer vias are experimentally characterized by using high-frequency S-parameter measurements. Test patterns are designed and fabricated using a package process. Then they are measured using Vector Network Analyzer (VNA) up to 25 GHz. Modeling a via as a circuit, its model parameters are determined. It is shown that the circuit model has excellent agreement with the measured S-parameters. The signal integrity of the lines with inter-layer vias is evaluated by using the developed circuit model. Thereby, it is shown that via may have a substantially deteriorative effect on the signal integrity of high-speed integrated circuits.

• Journal of IKEEE
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• v.20 no.3
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• pp.333-336
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• 2016

LIN (local interconnect network) is a standard low-speed serial communication protocol, and it was developed as an efficient sub-bus for automotive electronic modules. In this paper, a LIN controller was implemented in Verilog HDL, based on LIN ver. 2.2A. The implemented LIN controller was verified in FPGA, and it can be supplied as an IP to be integrated into SoC system. Its size is about 2,300 gates when synthesized in 0.18um technology.