• 제목/요약/키워드: interconnect

검색결과 569건 처리시간 0.021초

Redundancy TSV 연결 테스트를 위한 래퍼셀 설계 (Wrapper Cell Design for Redundancy TSV Interconnect Test)

  • 김화영;오정섭;박성주
    • 대한전자공학회논문지SD
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    • 제48권8호
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    • pp.18-24
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    • 2011
  • 칩의 적층 기술이 적용된 TSV기반 3D IC로 진화함에 따라 새로운 문제점이 발생하게 되었다. Bonding 이후 다이간 TSV가 제대로 연결되었는지 테스트하지만 Redundnacy TSV에 대해서는 테스트하지 않는다. 그러나 더 높은 수율을 얻기 위해서는 redundancy TSV에 대한 연결 테스트를 수행해야 한다. redundancy TSV의 연결을 테스트하고 진단하여 고장 있는 TSV를 대체함으로써 더 높은 수율을 얻을 수 있다. 본 논문에서는 TSV기반 3D IC에서 다이간의 TSV 연결 테스트뿐 아니라 redundancy TSV 테스트를 위한 래퍼셀을 제안하고자 한다. 제안하는 래퍼셀은 하드웨어로 설계하였을 시 기존의 테스트패턴을 그대로 사용할 수 있고, 소프트웨어 설계 시에는 면적을 최소화할 수 있다.

전기화학 기계적 연마를 이용한 Cu 배선의 평탄화 (Planarizaiton of Cu Interconnect using ECMP Process)

  • 정석훈;서헌덕;박범영;박재홍;정해도
    • 한국전기전자재료학회논문지
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    • 제20권3호
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    • pp.213-217
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    • 2007
  • Copper has been used as an interconnect material in the fabrication of semiconductor devices, because of its higher electrical conductivity and superior electro-migration resistance. Chemical mechanical polishing(CMP) technique is required to planarize the overburden Cu film in an interconnect process. Various problems such as dishing, erosion, and delamination are caused by the high pressure and chemical effects in the Cu CMP process. But these problems have to be solved for the fabrication of the next generation semiconductor devices. Therefore, new process which is electro-chemical mechanical polishing(ECMP) or electro-chemical mechanical planarization was introduced to solve the technical difficulties and problems in CMP process. In the ECMP process, Cu ions are dissolved electrochemically by the applying an anodic potential energy on the Cu surface in an electrolyte. And then, Cu complex layer are mechanically removed by the mechanical effects between pad and abrasive. This paper focuses on the manufacturing of ECMP system and its process. ECMP equipment which has better performance and stability was manufactured for the planarization process.

열 플라스마 용사법에 의해 코팅된 고체산화물 연료전지용 세라믹 연결재 특성 연구 (Characterization and Preparation of Ceramic Interconnect of SOFC by Thermal Plasma Spray Coating Process)

  • 박광연;임탁형;이승복;박석주;신동렬;송락현
    • 한국신재생에너지학회:학술대회논문집
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    • 한국신재생에너지학회 2009년도 추계학술대회 논문집
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    • pp.187-190
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    • 2009
  • $LaCrO_3$ series are the most common candidate materials for a ceramic interconnect for SOFC and the thermal expansion coefficient of these matches very well with that of YSZ electrolyte. In this study, characteristics of the coated films on the anode-support, which were formed by using $La_{0.8}Ca_{0.2}CrO_3$, $La_{0.8}Sr_{0.2}CrO_3$, $La_{0.8}Ca_{0.2}Co_{0.1}Cr_{0.9}O_3$ for ceramic interconnet for SOFC, were investigated. All powders showed single perovskite phase and the precursors had spherical shapes of $2{\mu}m{\sim}30{\mu}m$. According to SEM analysis, coated film of LCC on pretreated anode-support was more thicker, whereas the coated film on untreated anode-support was densely formed. As the results of electrical conductivity of anode-support coated with the ceramic interconnects, LCCC exhibited the most excellent electrical conductivity of 0.15S/cm at $750^{\circ}C$.

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박막 코팅을 이용한 SOFC 분리판 재료의 내산화성 향상 (Improvement of Oxidation-resisting Characteristic for SOFC Interconnect Material by Use of Thin Film Coating)

  • 이창보;배중면
    • 대한기계학회논문집B
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    • 제30권12호
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    • pp.1211-1217
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    • 2006
  • This study is focused on oxidation prevention of STS430, which is generally used as solid oxide fuel cell(SOFC) interconnect at intermediate operating temperatures with oxidation-proof coatings. Inconel, $La_{0.6}Sr_{0.4}CoO_3(LSCo)$ and $La_{0.6}Sr_{0.4}CoO_3(LSCr)$ were chosen as coating materials. Using a radio frequency magnetron sputtering method, each target material was deposited as thin film on STS430 and was analyzed to find out favorable conditions. In this study, LSCr-coated STS430 can reduce electrical resistance to 1/3 level, compared with uncoated STS430. Also, long-term durability test at $700^{\circ}C$ for 1000 hours tells that LSCr thin layer performs an important role to prohibit serious degradations. Superior oxidation-resistant characteristic of LSCr-coated STS430 is attributed to the inhibition of spinel structure formation such as $MnCr_2O_4$.

연결선에 기인한 시간지연의 정확한 모델 및 실험적 검증 (A New Accurate Interconnect Delay Model and Its Experiment Verification)

  • 윤성태;어영선;심종인
    • 대한전자공학회논문지SD
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    • 제37권9호
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    • pp.78-85
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    • 2000
  • 본 논문에서는 고속 VLSI 회로 내의 전송선에서 발생하는 전달지연시간을 계산하는 해석적 모델을 제시하고 그 모델의 정확성을 실험적으로 검증한다. 새로 제시한 모델은 표피효과, 근접효과 그리고 실리콘 기판에 의한 전성선 파라미터 변화를 고려하기 때문에 이들 영향을 반영한 새로운 인터커넥트 회로모델에 대하여 시간지연 모델을 구현한다. 모델의 정확성을 검증하기 위해 코플레너(coplanar)와 마이크로 스트립구조가 결합한 패턴의 모델을 0.35${\mu}m$ CMOS 공정을 사용하여 제작하였다. 이들 테스트 패턴에 대한 실험적 검증을 통하여 모델이 약 10% 이내의 오차범위에서 정확하다는 것을 보인다.

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Comprehensive Performance Analysis of Interconnect Variation by Double and Triple Patterning Lithography Processes

  • Kim, Youngmin;Lee, Jaemin;Ryu, Myunghwan
    • JSTS:Journal of Semiconductor Technology and Science
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    • 제14권6호
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    • pp.824-831
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    • 2014
  • In this study, structural variations and overlay errors caused by multiple patterning lithography techniques to print narrow parallel metal interconnects are investigated. Resistance and capacitance parasitic of the six lines of parallel interconnects printed by double patterning lithography (DPL) and triple patterning lithography (TPL) are extracted from a field solver. Wide parameter variations both in DPL and TPL processes are analyzed to determine the impact on signal propagation. Simulations of 10% parameter variations in metal lines show delay variations up to 20% and 30% in DPL and TPL, respectively. Monte Carlo statistical analysis shows that the TPL process results in 21% larger standard variation in delay than the DPL process. Crosstalk simulations are conducted to analyze the dependency on the conditions of the neighboring wires. As expected, opposite signal transitions in the neighboring wires significantly degrade the speed of signal propagation, and the impact becomes larger in the C-worst metals patterned by the TPL process compared to those patterned by the DPL process. As a result, both DPL and TPL result in large variations in parasitic and delay. Therefore, an accurate understanding of variations in the interconnect parameters by multiple patterning lithography and adding proper margins in the circuit designs is necessary.

Evaluation of STS 430 and STS 444 for SOFC Interconnect Applications

  • Kim, S.H.;Huh, J.Y.;Jun, J.H.;Kim, D.H.;Jun, J.H.
    • Corrosion Science and Technology
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    • 제6권1호
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    • pp.1-6
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    • 2007
  • Ferritic stainless steels for the SOFC interconnect applications are required to possess not only a good oxidation resistance, but also a high electrical conductivity of the oxide scale that forms during exposure at the SOFC operating environment. In order to understand the effects of alloying elements on the oxidation behavior of ferritic stainless steels and on the electrical properties of oxide scales, two kinds of commercial ferritic stainless steels, STS 430 and STS 444, were investigated by performing isothermal oxidations at $800^{\circ}C$ in a wet air containing 3% $H_{2}O$. The results showed that STS 444 was superior to STS 430 in both of the oxidation resistance and the area specific resistance. Although STS 444 contained a less amount of Mn for the $(Mn,Cr)_{3}O_{4}$ spinel formation than STS 430, the minor alloying elements of Al and Mo in STS 444, which were accumulated in the base metal region adjacent the scale, were suggested to reduce the scale growth rate and to enhance the scale adherence to the base metal.

글로벌 배선 적용을 위한 UV 패턴성과 UV 경화성을 가진 폴리실록산 (Organic-inorganic Hybrid Dielectric with UV Patterning and UV Curing for Global Interconnect Applications)

  • 송창민;박해성;서한결;김사라은경
    • 마이크로전자및패키징학회지
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    • 제25권4호
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    • pp.1-7
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    • 2018
  • As the performance and density of IC (integrated circuit) devices increase, power and signal integrities in the global interconnects of advanced packaging technologies are becoming more difficult. Thus, the global interconnect technologies should be designed to accommodate increased input/output (I/O) counts, improved power grid network integrity, reduced RC delay, and improved electrical crosstalk stability. This requirement resulted in the fine-pitch interconnects with a low-k dielectric in 3D packaging or wafer level packaging structure. This paper reviews an organic-inorganic hybrid material as a potential dielectric candidate for the global interconnects. An organic-inorganic hybrid material called polysiloxane can provide spin process without high temperature curing, an excellent dielectric constant, and good mechanical properties.

확장성 신뢰성 갖춘 양자 컴퓨터를 위한 CMOS 기반 제어 및 센싱 회로 기술 (CMOS Interconnect Electronics Architecture for Reliable and Scalable Quantum Computer)

  • 김주성;한정환;남재원;조건희
    • 전기전자학회논문지
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    • 제27권1호
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    • pp.12-18
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    • 2023
  • 각각의 큐빗(qubit)을 개별적으로 상온의 제어 회로에 연결하는 현재의 회로 기술은 양자 컴퓨터의 확장성, 신뢰성을 갖추는 데 있어 한계를 가지고 있으며, 집적도 측면에서 극저온의 CMOS 기술 기반 인터커넥트 회로 기술을 통해 기존 기술 대비 인터커넥트의 복잡도, 시스템 안정도 및 사이즈, 그리고 가격 경쟁력을 획기적으로 개선할 수 있을 것으로 기대되고 있다. 외부의 전기적 자극에 민감하며 양자 상태를 일정 시간 이상 유지할 수 없는 큐빗의 특성으로 인한 문제를 극복하고, 확장성과 신뢰성을 양자 컴퓨터 실현을 위한 CMOS 기술 기반 집적화된 센싱 및 제어 회로 기술에 대해 소개한다.