• Journal of the Institute of Electronics Engineers of Korea SD
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• v.48 no.8
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• pp.18-24
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• 2011

A new problem happens with the evolution of TSV based 3D IC design. The bonding process takes place which follows with the testing of design for proper connectivity in the absence of TSV redundancy. In order to achieve good yield, the design should be tested with redundancy TSV. This paper presents a wrapper cell design for redundancy TSV interconnect test. The design for test technique, in terms of hardware and software perspectives is described. The wrapper cell with hardware design can use original test patterns. However, software design has less area overhead.

• Journal of the Korean Institute of Electrical and Electronic Material Engineers
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• v.20 no.3
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• pp.213-217
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• 2007

Copper has been used as an interconnect material in the fabrication of semiconductor devices, because of its higher electrical conductivity and superior electro-migration resistance. Chemical mechanical polishing(CMP) technique is required to planarize the overburden Cu film in an interconnect process. Various problems such as dishing, erosion, and delamination are caused by the high pressure and chemical effects in the Cu CMP process. But these problems have to be solved for the fabrication of the next generation semiconductor devices. Therefore, new process which is electro-chemical mechanical polishing(ECMP) or electro-chemical mechanical planarization was introduced to solve the technical difficulties and problems in CMP process. In the ECMP process, Cu ions are dissolved electrochemically by the applying an anodic potential energy on the Cu surface in an electrolyte. And then, Cu complex layer are mechanically removed by the mechanical effects between pad and abrasive. This paper focuses on the manufacturing of ECMP system and its process. ECMP equipment which has better performance and stability was manufactured for the planarization process.

• 한국신재생에너지학회:학술대회논문집
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• 2009.11a
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• pp.187-190
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• 2009

$LaCrO_3$ series are the most common candidate materials for a ceramic interconnect for SOFC and the thermal expansion coefficient of these matches very well with that of YSZ electrolyte. In this study, characteristics of the coated films on the anode-support, which were formed by using $La_{0.8}Ca_{0.2}CrO_3$, $La_{0.8}Sr_{0.2}CrO_3$, $La_{0.8}Ca_{0.2}Co_{0.1}Cr_{0.9}O_3$ for ceramic interconnet for SOFC, were investigated. All powders showed single perovskite phase and the precursors had spherical shapes of $2{\mu}m{\sim}30{\mu}m$. According to SEM analysis, coated film of LCC on pretreated anode-support was more thicker, whereas the coated film on untreated anode-support was densely formed. As the results of electrical conductivity of anode-support coated with the ceramic interconnects, LCCC exhibited the most excellent electrical conductivity of 0.15S/cm at $750^{\circ}C$.

• Transactions of the Korean Society of Mechanical Engineers B
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• v.30 no.12 s.255
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• pp.1211-1217
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• 2006

This study is focused on oxidation prevention of STS430, which is generally used as solid oxide fuel cell(SOFC) interconnect at intermediate operating temperatures with oxidation-proof coatings. Inconel, $La_{0.6}Sr_{0.4}CoO_3(LSCo)$ and $La_{0.6}Sr_{0.4}CoO_3(LSCr)$ were chosen as coating materials. Using a radio frequency magnetron sputtering method, each target material was deposited as thin film on STS430 and was analyzed to find out favorable conditions. In this study, LSCr-coated STS430 can reduce electrical resistance to 1/3 level, compared with uncoated STS430. Also, long-term durability test at $700^{\circ}C$ for 1000 hours tells that LSCr thin layer performs an important role to prohibit serious degradations. Superior oxidation-resistant characteristic of LSCr-coated STS430 is attributed to the inhibition of spinel structure formation such as $MnCr_2O_4$.

• Journal of the Institute of Electronics Engineers of Korea SD
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• v.37 no.9
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• pp.78-85
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• 2000

A new analytical VLSI interconnect delay model is presented and its accuracy is experimentally verified. In the model, the transmission line parameter variations due to skin effect, proximity effect, and silicon substrate effect are taken into account. That is, the circuit model of the interconnect line that includes these effects is newly developed and analyzed. For the model verification, test patterns combined the coplanar structure with microstrip were designed by using 0.35${\mu}m$ CMOS process technology. It is shown that the accuracy of the model is less than about 10% error.

• JSTS:Journal of Semiconductor Technology and Science
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• v.14 no.6
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• pp.824-831
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• 2014

In this study, structural variations and overlay errors caused by multiple patterning lithography techniques to print narrow parallel metal interconnects are investigated. Resistance and capacitance parasitic of the six lines of parallel interconnects printed by double patterning lithography (DPL) and triple patterning lithography (TPL) are extracted from a field solver. Wide parameter variations both in DPL and TPL processes are analyzed to determine the impact on signal propagation. Simulations of 10% parameter variations in metal lines show delay variations up to 20% and 30% in DPL and TPL, respectively. Monte Carlo statistical analysis shows that the TPL process results in 21% larger standard variation in delay than the DPL process. Crosstalk simulations are conducted to analyze the dependency on the conditions of the neighboring wires. As expected, opposite signal transitions in the neighboring wires significantly degrade the speed of signal propagation, and the impact becomes larger in the C-worst metals patterned by the TPL process compared to those patterned by the DPL process. As a result, both DPL and TPL result in large variations in parasitic and delay. Therefore, an accurate understanding of variations in the interconnect parameters by multiple patterning lithography and adding proper margins in the circuit designs is necessary.

• Corrosion Science and Technology
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• v.6 no.1
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• pp.1-6
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• 2007

Ferritic stainless steels for the SOFC interconnect applications are required to possess not only a good oxidation resistance, but also a high electrical conductivity of the oxide scale that forms during exposure at the SOFC operating environment. In order to understand the effects of alloying elements on the oxidation behavior of ferritic stainless steels and on the electrical properties of oxide scales, two kinds of commercial ferritic stainless steels, STS 430 and STS 444, were investigated by performing isothermal oxidations at $800^{\circ}C$ in a wet air containing 3% $H_{2}O$. The results showed that STS 444 was superior to STS 430 in both of the oxidation resistance and the area specific resistance. Although STS 444 contained a less amount of Mn for the $(Mn,Cr)_{3}O_{4}$ spinel formation than STS 430, the minor alloying elements of Al and Mo in STS 444, which were accumulated in the base metal region adjacent the scale, were suggested to reduce the scale growth rate and to enhance the scale adherence to the base metal.

• Journal of the Microelectronics and Packaging Society
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• v.25 no.4
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• pp.1-7
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• 2018

As the performance and density of IC (integrated circuit) devices increase, power and signal integrities in the global interconnects of advanced packaging technologies are becoming more difficult. Thus, the global interconnect technologies should be designed to accommodate increased input/output (I/O) counts, improved power grid network integrity, reduced RC delay, and improved electrical crosstalk stability. This requirement resulted in the fine-pitch interconnects with a low-k dielectric in 3D packaging or wafer level packaging structure. This paper reviews an organic-inorganic hybrid material as a potential dielectric candidate for the global interconnects. An organic-inorganic hybrid material called polysiloxane can provide spin process without high temperature curing, an excellent dielectric constant, and good mechanical properties.

• Journal of IKEEE
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• v.27 no.1
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• pp.12-18
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• 2023

The current circuit technology that individually connects each qubit to a control circuit at room temperature has limitations in achieving scalability and reliability of a quantum computer. With the advent of cryogenic CMOS interconnect electronics, it is expected to dramatically improve the interconnect complexity, system reliability and size, and price. In this paper, we introduce the CMOS integrated sensing and control technology platform overcoming the problems caused by the fragile and sensitive characteristics of qubit.

• Proceedings of the KIPE Conference
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• 1996.06a
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• pp.60-62
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• 1996