• Journal of the Korean Institute of Electrical and Electronic Material Engineers
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• v.27 no.11
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• pp.686-689
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• 2014

Electrostatic discharge has been considered as a major reliability problem in the semiconductor industry. ESD reliability is an important issue for these products. Therefore, each I/O (Input/Output) PAD must be designed with a protection circuitry that creates a low impedance discharge path for ESD current. This paper presents a novel Lateral Insulated Gate Bipolar (LIGBT)-based ESD protection circuit with latch-up immunity and high robustness. The proposed circuit is fabricated by using 0.18 um BCD (bipolar-CMOS-DMOS) process. Also, TLP (transmission line pulse) I-V characteristic of proposed circuit is measured. In the result, the proposed ESD protection circuit has latch-up immunity and high robustness. These characteristics permit the proposed circuit to apply to power clamp circuit. Consequently, the proposed LIGBT-based ESD protection circuit with a latch-up immune characteristic can be applied to analog integrated circuits.

• Proceedings of the Korean Institute of Communication Sciences Conference
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• 1983.04a
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• pp.45-47
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• 1983

In integrated circuit, for a saving in total chip area per circuit, stably high value resistor was fabricated. Hence this paper explained that the measurement and fabrication of high value semiconductor resistor using ITO thin film. It is also used special material and new method fabrication.

• 제어로봇시스템학회:학술대회논문집
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• 2003.10a
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• pp.73-77
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• 2003

This paper presents a high-speed algorithmic analog-to-digital converter (ADC), which is based on gray coding. The realization method makes use of a two-input maximum circuit to provide a high-speed operation and a low-distortion in the transfer characteristic. The proposed ADC based on the CMOS integrated circuit technique is simple and suitable for implementing a highresolution ADC. The performances of the proposed circuit were studied using the PSPICE analog simulation program. The simulation-results verifying the circuit performances are agreed with the expected values.

• Journal of information and communication convergence engineering
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• v.7 no.1
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• pp.62-65
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• 2009

In this paper, the temperature characteristics of full CMOS FLL(frequency locked loop) re analyzed. The FLL circuit is used to generate an output signal that tracks an input efference signal. The locking time of FLL is short compared to PLL(phase locked loop) circuit because the output signal of FLL is synchronized only in frequency. Also the FLL s designed to allow the circuit to be fully integrated. The FLL circuit is composed two VCs, two buffers, a VCO and two frequency dividers. The temperature variation of frequency divider, FVC and buffer cancelled because the circuit structure. is the same and he temperature effect is cancelled by the comparator. Simulation results are shown to illustrate the performance of the designed FLL circuit with temperature.

• Journal of Electrical Engineering and Technology
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• v.6 no.3
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• pp.408-413
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• 2011

In this paper, a real-coefficient approach to Adaptive Frequency Sampling (AFS) technique is developed for efficient equivalent circuit modeling of RF components. This proposed method is advantageous than the vector fitting technique and the conventional AFS method in terms of fewer samples leading to a lower order of a rational function on a given data and to a direct conversion to an equivalent circuit for PSPICE(Personal Simulation Program with Integrated Circuit Emphsis) simulation, respectively. To validate the proposed method, the distributed equivalent circuit of a presented multi-layered RF low-pass filter is obtained using the proposed real-coefficient AFS, and then comparisons with EM simulation and circuit simulation for the device under consideration are achieved.

• Tribology and Lubricants
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• v.29 no.3
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• pp.143-148
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• 2013

In this study, several sensor parts used to obtain better signal stability are designed, a separate control circuit for the sensor is developed, and the results obtained using this control circuit are analyzed. The capacitances of the whole sensor system are measured using the control circuit connected to an improved flexible printed circuit board and an asymmetric dual sensor coated with a ceramic material. To realize good discrimination for a small change in the measured capacitance as the engine oil deteriorates, a commercial application-specific integrated circuit is installed on the control circuit as a capacitance-to-digital converter. The absolute error of a measured signal is found to be approximately ${\pm}4fF$.

• Journal of Korea Society of Digital Industry and Information Management
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• v.9 no.2
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• pp.55-61
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• 2013

A field-programmable gate array (FPGA) is an integrated circuit designed to be configured by a customer or a designer after manufacturing. The FPGA configuration is generally specified using a hardware description language (HDL), similar to that used for an application-specific integrated circuit (ASIC) (circuit diagrams were previously used to specify the configuration, as they were for ASICs, but this is increasingly rare). Contemporary FPGAs have large resources of logic gates and RAM blocks to implement complex digital computations. In this paper, we implement a system of digital instrumentation using FPGA. This system consists of the trigger part, memory address controller part, control FSM part, Encoder part, LCD controller part. The hardware implement using FPGA and the verification of the operation is done in a PC simulation. The proposed hardware was mapped into Cyclone III EP2C5Q208 from Altera and used 1,700(40%) of Logic Element (LE). The implemented circuit used 24,576-bit memory element with 6-bit input signal. The result from implementing in hardware (FPGA) could operate stably in 140MHz.

• Journal of information and communication convergence engineering
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• v.11 no.1
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• pp.56-61
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• 2013

Modern integrated circuits (ICs) are becoming an integrated parts of analog, digital, and radio frequency (RF) circuits. Testing these RF circuits on a chip is an important task, not only for fabrication quality control but also for tuning RF circuit elements to fit multi-standard wireless systems. In this paper, RF test circuits suitable for embedded testing are introduced: RF power detectors, power control circuits, directional couplers, and six-port reflectometers. Various types of embedded RF power detectors are reviewed. The conventional approach and our approach for the RF power control circuits are compared. Also, embedded tunable active directional couplers are presented. Then, six-port reflectometers for embedded RF testing are introduced including a 77-GHz six-port reflectometer circuit in a 130 nm process. This circuit demonstrates successful calibrated reflection coefficient simulation results for 37 well distributed samples in a Smith chart. The details including the theory, calibration, circuit design techniques, and simulations of the 77-GHz six-port reflectometer are presented in this paper.

• 한국ITS학회:학술대회논문집
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• v.2007 no.10
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• pp.144-148
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• 2007

• Journal of the Korean Institute of Telematics and Electronics
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• v.24 no.6
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• pp.1056-1067
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• 1987

This paper presents a design procedure for building block integrated circuits that is based on the digraph relaxation model. A set of optimization procedure is prosented for a minimum area and routing-fecsible placement of IC building blocks. Chip area optimization is subject to perimeter and area constraints on the component rectangles in the dissection.