The Layout Design of Structured Building Block Integrated Circuit

조립된 Building Block IC의 설계디자인의 문제

This paper presents a design procedure for building block integrated circuits that is based on the digraph relaxation model. A set of optimization procedure is prosented for a minimum area and routing-fecsible placement of IC building blocks. Chip area optimization is subject to perimeter and area constraints on the component rectangles in the dissection.