• Proceedings of the IEEK Conference
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• 2004.06b
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• pp.419-422
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• 2004

A sensing scheme for current-mode magneto-resistance random access memory (MRAM) with a 1T1MTJ cell structure is proposed. Magnetic tunnel junction (MTJ) resistance, which is HIGH or LOW, is converted to different cell currents during READ operation. The cell current is then amplified to be evaluated by the reference cell current. In this scheme, conventional bit line sense amplifiers are not required and the operation is less sensitive to voltage noise than that of voltage-mode circuit is. It has been confirmed with HSPICE simulations using a 0.35-${\mu}m$ 2-poly 4-metal CMOS technology.

• Proceedings of the KIPE Conference
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• 2008.06a
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• pp.406-409
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• 2008

This paper presents the integrated magnetic circuit designing method for phase shift full bridge(PSFB) converter. The integrated magnetic circuit is implemented on redesigned of EI core. The transformer windings are located on center leg and the two inductors are located on the outer legs with air gap. Based on the equivalent circuit model, the principle of operation of the PSFB converter is explained. The operation and performance of the proposed circuit are verified on a 1.2 kW prototype converter. The analysis and design of the integrated magnetic circuit is verified through the experimental and simulation results.

• Transactions on Electrical and Electronic Materials
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• v.14 no.5
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• pp.235-241
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• 2013

A low power CMOS control circuit is applied in an integrated DC-DC buck converter. The integrated converter is composed of a feedback control circuit and power block with 0.35 ${\mu}m$ CMOS process. A current-sensing circuit is integrated with the sense-FET method in the control circuit. In the current-sensing circuit, a current-mirror is used for a voltage follower in order to reduce power consumption with a smaller chip-size. The N-channel MOS acts as a switching device in the current-sensing circuit where the sensing FET is in parallel with the power MOSFET. The amplifier and comparator are designed to obtain a high gain and a fast transient time. The converter offers well-controlled output and accurately sensed inductor current. Simulation work shows that the current-sensing circuit is operated with an accuracy of higher than 90% and the transient time of the error amplifier is controlled within $75{\mu}sec$. The sensing current is in the range of a few hundred ${\mu}A$ at a frequency of 0.6~2 MHz and an input voltage of 3~5 V. The output voltage is obtained as expected with the ripple ratio within 1%.

• 제어로봇시스템학회:학술대회논문집
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• 2003.10a
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• pp.970-973
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• 2003

Abstract An idea to redce the direct-path short circuit current of the CMOS digital integrated circuit is present. The sample circuit model of the CMOS digital circuit is the CMOS current-control digital output driver circuit, which are also suitable for the low voltage supply integrated circuits as the simple digital inverter, are present in this title. The circuit consists of active MOS load as the current control source, which construct from the saturated n-channel and p-channel MOSFET and the general CMOS inverter circuits. The saturated MOSFET bias can control the output current and the frequency response of the circuit. The experimental results show that lower short circuit current control can make the lower frequency response of the circuit.

• Proceedings of the IEEK Conference
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• 2006.06a
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• pp.529-530
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• 2006

An efficient sensing scheme adoptable in DC-DC converter is described. The output voltage of the whole DC-DC converter is fed back to the input voltage of the sensor. The comparison in the sensor is accomplished by a current push-pull action. With a fixed reference, the comparator can be embodied based on (W/L) ratios. The current-mode scheme benefits the system better than a conventional voltage-mode one in terms of small area, low power consumption.

• Proceedings of the IEEK Conference
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• 2006.06a
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• pp.521-522
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• 2006

This paper presents behavioral models using SIMULINK and Verilog-a for a PLL based fractional-N frequency synthesizer. The SIMULINK modeling was built in the frequency-time mixed domain whereas the Verilog-a modeling was built purely in the time domain. The simulated results of the two models were verified to show the same performance within the error tolerance. This top-down design method can provide the readiness for the transistor-level design.

• Proceedings of the IEEK Conference
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• 2006.06a
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• pp.523-524
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• 2006

Successive approximation A/D converters have an advantage of small chip area and simple algorithm. We propose an improved non-redundant successive approximation register (SAR) which can be incorporated in successive approximation A/D converters. The proposed SAR validates the preset state as the $1^{st}$ reference voltage to the comparator. Two redundant clock cycles in the typical design could be eliminated in the proposed A/D converter.

• Proceedings of the IEEK Conference
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• 2006.06a
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• pp.625-626
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• 2006

An Ultra low power super-regenerative oscillator was implemented with on-chip inductor and quench signal generator. The super-regenerative oscillator detects the signal level as low as -70dBm while consuming only 0.48mA at 1.5V supply voltage. These results indicate that the super-regenerative oscillator can be outstanding candidate the simple, ultra low power receiver design.

• Journal of the Korean Institute of Illuminating and Electrical Installation Engineers
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• v.25 no.2
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• pp.80-86
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• 2011

This paper presents an integrated variable amplitude high voltage pulse generation circuit with low power and small size for driving industrial piezoelectric printer heads. To solve the problems of large size and power overhead of conventional pulse generators that usually assembled with multiple high-cost discrete ICs on a PCB board, we have designed a new integrated circuit (IC) chip. Since all the functions are integrated on to a single-chip it can achieve low cost and control the high-voltage output pulse with variable amplitudes as well. It can also digitally control the rising and falling times of an output high voltage pulse by using programmable RC time control of the output buffer. The proposed circuit has been designed and simulatedd in a 180[nm] Bipolar-CMOS-DMOS (BCD) technology using HSPICE and Cadence Virtuoso Tools. The proposed single-chip pulse generation circuit is suitable for use in industrial printer heads requiring a variable high voltage driving capability.

• Journal of the Semiconductor & Display Technology
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• v.17 no.1
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• pp.21-26
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• 2018

In this paper, a multiple coupling inductor with expandable-integrated magnetic structure was proposed to enable miniaturization of external switched mode power supply (SMPS) for a large display. Inductance formula of the proposed inductor structure was derived through magnetic circuit analysis for a simple inductance designing process. The proposed inductor was applied into a 1kW class interleaved bridgeless power factor correction circuit which requires four inductors, and experimental steady state result of the circuit was compared. According to the experimental result, it was found that the proposed multiple coupling inductor shows the electrical characteristics that can replace the conventional separated inductors and is suitable for miniaturization of the SMPS since the circuit configuration is possible with one shared inductor.