• 한국전기전자재료학회:학술대회논문집
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• 한국전기전자재료학회 2003년도 춘계학술대회 논문집 센서 박막재료 반도체 세라믹
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• pp.170-173
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• 2003

In this paper, we proposed a new bulk LDMOS structure which can be used for RF application, and its fabrication steps were introduced. The simulated devices consist of three types: Bulk device, SLB(SOI Like Bulk), and SOI device. As a result of process and device simulation, we showed electrical characteristics, such as threshold voltage, subthreshold slope, DIBL(Drain Induced Barrier Lowering), off-state current, and breakdown voltage. In this simulation study, the lattice temperature model was adopted to see the device characteristics with lattice temperature during the operation. SLB device structure showed the best breakdown characteristics among the other structures. The breakdown voltage of SLB structure is about 9V, that of bulk is 7V, and that of SOI is 8V.

• 한국전기전자재료학회:학술대회논문집
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• 한국전기전자재료학회 2002년도 제4회 영호남학술대회 논문집
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• pp.58-63
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• 2002

For the experiment the four types of spacer were distinguished by arrangement. The flashover characteristic on each types of spacer was investigated and the flashover phenomena were observed to understand breakdown mechanism in liquid nitrogen($LN_{2}$). The spacer should be placed interior coil as an insulator, a cooling channel and s supporter of structures. The simulated electrode used in the experiment was made from five turns of HTS tape. Experimental results revealed that multi-layer and barrier effects did work well in Air but did not in $LN_{2}$. These result suggested that the flashover in LN2 caused by the bubbles due to partial discharge at micro gap, g. The flashover characteristics decreased to 70% when g is 0.2 mm. The degradation was improved by even treatment on surface of coil electrode.

• 전자공학회논문지A
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• 제31A권12호
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• pp.56-63
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• 1994

The effects of sulfur treatments on the barrier heithts of Schottky contacts and the interface-state density of metal-insulator-semiconductor (MIS) capacitors on InP have been investigated. Schottky contacts were formed by the evaporation of Al, Au, and Pt on n-InP substrate before and after (NH$_{4}$)$_{2}$S$_{x}$ treatments, respectively. The barrier height of InP Schottky contacts was measured by their current-voltage (I-V) and capacitance-voltage (C_V) characteristics. We observed that the barrier heights of Schottky contacks on bare InP were 0.35~0.45 eV nearly independent of the metal work function, which is known to be due to the surface Fermi level pinning. In the case of sulfur-treated Au/InP ar Pt/InP Schottky diodes, However, the barrier heights were not only increased above 0.7 eV but also highly dependent on the metal work function. We have also investigated effects of (NH$_{4}$)$_{2}$S$_{x}$ treatments on the distribution of interface states in Si$_{3}$N$_{4}$InP MIS diodes where Si$_{3}$N$_{4}$ was provided by plasma enhanced chemical vapor deposition (PECVD). The typical value of interface-state density extracted feom 1 MHz C-V curve of sulfur-treated SiN$_{x}$/InP MIS diodes was found to be the order of 5${\times}10^{10}cm^{2}eV^{1}$. This value is much lower than that of MiS diodes made on bare InP surface. It is certain, therefore, that the (NH$_{4}$)$_{2}$S$_{x}$ treatment is a very powerful tool to enhance the barrier heights of Au/n-InP and Pt/n-InP Schottky contacts and to reduce the density of interface states in SiN$_{x}$/InP MIS diode.

• 한국진공학회:학술대회논문집
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• 한국진공학회 2009년도 제38회 동계학술대회 초록집
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• pp.31-32
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• 2010

In our previous reports [1-3], electron transport for the switching and memory devices using alkyl thiol-tethered Ru-terpyridine complex compounds with metal-insulator-metal crossbar structure has been presented. On the other hand, among organic memory devices, a memory based on the OFET is attractive because of its nondestructive readout and single transistor applications. Several attempts at nonvolatile organic memories involve electrets, which are chargeable dielectrics. However, these devices still do not sufficiently satisfy the criteria demanded in order to compete with other types of memory devices, and the electrets are generally limited to polymer materials. Until now, there is no report on nonvolatile organic electrets using nano-interfaced organic monomer layer as a dielectric material even though the use of organic monomer materials become important for the development of molecularly interfaced memory and logic elements. Furthermore, to increase a retention time for the nonvolatile organic memory device as well as to understand an intrinsic memory property, a molecular design of the organic materials is also getting important issue. In this presentation, we report on the OFET memory device built on a silicon wafer and based on films of pentacene and a SiO2 gate insulator that are separated by organic molecules which act as a gate dielectric. We proposed push-pull organic molecules (PPOM) containing triarylamine asan electron donating group (EDG), thiophene as a spacer, and malononitrile as an electron withdrawing group (EWG). The PPOM were designed to control charge transport by differences of the dihedral angles induced by a steric hindrance effect of side chainswithin the molecules. Therefore, we expect that these PPOM with potential energy barrier can save the charges which are transported to the nano-interface between the semiconductor and organic molecules used as the dielectrics. Finally, we also expect that the charges can be contributed to the memory capacity of the memory OFET device.[4]

• 한국산학기술학회논문지
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• 제19권6호
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• pp.709-714
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• 2018

반도체소자의 접합특성에 따라서 분극의 특성이 달라지는 원인을 조사하였다. 반도체소자의 접합특성은 최종적인 반도체소자의 효율과 관련되기 때문에 중요한 요소이며, 효율을 높이기 위해서는 반도체접합 특성을 이해하는 것은 매우 중요하다. 다양한 성질의 접합을 얻기위하여 n형의 실리콘 위에 절연물질인 carbon doped silicon oxide (SiOC) 박막을 증착하였으며, 아르곤 (Ar) 유량에 따라서 반도체기판의 특성이 달라지는 것을 확인하였다. 전도체인 tin doped zinc oxide (ZTO) 박막을 절연체인 SiOC 위에 증착하여 소자의 전도성을 살펴보았다. SiOC 박막의 특성은 플라즈마에 의하여 이온화현상이 일어날 때 Ar 유량에 따라서 이온화되는 경향이 달라지면서 반도체 계면에서의 공핍현상이 달라졌으며, 공핍층 형성이 많이 일어나는 곳에서 쇼키접합 특성이 잘 형성되는 것을 확인하였다. 아르곤 가스의 유량이 많은 경우 이온화 반응이 많이 일어나고 따라서 접합면에서 전자 홀쌍의 재결합반응에 의하여 전하들이 없어지게 되면 절연특성이 좋아지고 공핍층의 전위장벽이 증가되며, 쇼키접합의 형성이 유리해졌다. 쇼키접합이 잘 이루어지는 SiOC 박막에서 ZTO를 증착하였을 때 SiOC와 ZTO 사이의 계면에서 전하들이 재결합되면서 전기적으로 안정된 ZTO 박막을 형성하고, ZTO의 전도성이 증가되었다. 두께가 얇은 반도체소자에서 흐르는 낮은 전류를 감지하기 위해서는 쇼키접합이 이루어져야 하며, 낮은 전류만으로도 전기신호의 품질이 우수해지고 또한 채널층인 ZTO 박막에서의 전류의 발생도 많아지는 것을 확인하였다.

• 한국전기전자재료학회논문지
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• 제37권1호
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• pp.48-55
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• 2024

The changes in threshold voltage and DIBL were investigated for changes in remanent polarization P_r and coercive field E_c, which determine the characteristics of the P-E hysteresis curve of ferroelectric in NCFET (negative capacitance FET). The threshold voltage and DIBL (drain-induced barrier lowering) were observed for a junctionless double gate MOSFET using a gate oxide structure of MFMIS (metal-ferroelectric-metal-insulator-semiconductor). To obtain the threshold voltage, series-type potential distribution and second derivative method were used. As a result, it can be seen that the threshold voltage increases when P_r decreases and E_c increases, and the threshold voltage is also maintained constant when the P_r/E_c is constant. However, as the drain voltage increases, the threshold voltage changes significantly according to P_r/E_c, so the DIBL greatly changes for P_r/E_c. In other words, when P_r/E_c=15 pF/cm, DIBL showed a negative value regardless of the channel length under the conditions of ferroelectric thickness of 10 nm and SiO₂ thickness of 1 nm. The DIBL value was in the negative or positive range for the channel length when the P_r/E_c is 25 pF/cm or more under the same conditions, so the condition of DIBL=0 could be obtained. As such, the optimal condition to reduce short channel effects can be obtained since the threshold voltage and DIBL can be adjusted according to the device dimension of NCFET and the P_r and E_c of ferroelectric.

• Journal of Electrical Engineering and information Science
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• 제3권2호
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• pp.261-266
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• 1998

This paper describes the fabrication and characterization of dual-polysilicon gated surface channel 0.1$\mu\textrm{m}$ CMOSFETs using BF2 and arsenic as channel dopants. We have used and LDD structure and 40${\AA}$ gate oxide as an insulator. To suppress short channel effects down to 0.1$\mu\textrm{m}$ channel length, shallow source/drain extensions implemented by low energy implantation and SSR(Super Steep Retrograde) channel structure were used. The threshold voltages of fabricated CMOSFETs are 0.6V. The maximum transconductance of nMOSFET is 315${\mu}$S/$\mu\textrm{m}$, and that of pMOSFET is 156 ${\mu}$S/$\mu\textrm{m}$. The drain saturation current of 418 ${\mu}$A/$\mu\textrm{m}$, 187${\mu}$A/$\mu\textrm{m}$ are obtained. Subthreshold swing is 85mV/dec and 88mV/dec, respectively. DIBL(Drain Induced Barrier Lowering) is below 100mV. In the device with 2000${\AA}$ thick gate polysilicon, depletion in polysilicon near the gate oxide results in an increase of equivalent gate oxide thickness and degradation of device characteristics. The gate delay time is measured to be 336psec at operation voltage of 2V.

• Transactions on Electrical and Electronic Materials
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• 제8권1호
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• pp.36-40
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• 2007

Inorganic layers, such as SiOxNy and SiOx deposited using plasma sublimation method, were tested as passivation layer for organic thin-film-transistors (OTFTs). OTFTs with bottom-gate and bottom-contact structure were fabricated using pentacene as organic semiconductor and an organic gate insulator. SiOxNy layer gave little change in characteristics of OTFTs, but SiOx layer degraded the performance of OTFTs severely. Inferior barrier properties related to its lower film density, higher water vapor transmission rate (WVTR) and damage due to process environment of oxygen of SiOx film could explain these results. Polyurea and polyvinyl acetates (PVA) were tested as organic passivation layers also. PVA showed good properties as a buffer layer to reduce the damage come from the vacuum deposition process of upper passivation layers. From these results, a multilayer structure with upper SiOxNy film and lower PVA film is expected to be a superior passivation layer for OTFTs.

• 한국초전도학회:학술대회논문집
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• 한국초전도학회 2000년도 High Temperature Superconductivity Vol.X
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• pp.189-192
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• 2000

We fabricated rapid single-flux-quantum RS flip-flop circuits with and without Y$_1$Ba$_2$Cu$_3$O$_{7-{\delta}}$(YBCO) ground plane. The circuit consists of SNS-type ramp-edge Josephson junctions that have cobalt-doped YBCO and Sr$_2$AITaO$_6$(SAT) for barrier layer and insulator layer, respectively. The fabricated Josephson junction showed a typical RSJ-like current-voltage(I-V) characteristics above 50K. We sucessfuly demonstrated RS flip-flop at temperatures around 50K. The RS flip-flop fabricated on ground plane showed more definite set and reset state in voltage-flux(V-${\phi}$) modulation curve for read SQUID, which may be attributed to a shielding effect of the YBCO ground plane.

• JSTS:Journal of Semiconductor Technology and Science
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• 제4권1호
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• pp.52-62
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• 2004

In this paper we look at the effect of Fringe-Enhanced-Barrier-lowering (FEBL) for high-K dielectric MOSFETs and the dependence of FEBL on various technological parameters (spacer dielectrics, overlap length, dielectric stack, S/D junction depth and dielectric thickness). We show that FEBL needs to be contained in order to maintain the performance advantage with scaled high-K dielectric MOSFETs. The degradation in high-K dielectric MOSFETs is also identified as due to the additional coupling between the drain-to-source that occurs through the gate insulator, when the gate dielectric constant is significantly higher than the silicon dielectric constant. The technology parameters required to minimize the coupling through the high-K dielectric are identified. It is also shown that gate dielectric stack with a low-K material as bottom layer (very thin $SiO_2$ or oxy-nitride) will be helpful in minimizing FEBL. The circuit performance issues with high-K MOS transistors are also analyzed in this paper. An optimum range of values for the dielectric constant has been identified from the delay and the energy dissipation point of view. The dependence of the optimum K for different technology generations has been discussed. Circuit models for the parasitic capacitances in high-K transistors, by incorporating the fringing effects, have been presented.