• 한국정보통신설비학회:학술대회논문집
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• 한국정보통신설비학회 2008년도 정보통신설비 학술대회
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• pp.218-222
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• 2008

RF power amplifier requires linearization in order to reduce adjacent channel interference. And most of the existing linearization algorithms assume that a PA has memory-less nonlinearity. But for the wider bandwidth signal, the memory effect of PA cannot be ignored. This paper investigates digital pre-distortion by use of a memory polynomial model which compensates for amplifier nonlinearity and memory effect. The look-up table based implementation scheme is used to reduce the computational complexity of the pre-distortion block. The linearization performance is demonstrated on wideband CDMA signal and class AB high power amplifier.

• International Journal of Internet, Broadcasting and Communication
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• 제10권4호
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• pp.6-11
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• 2018

As embedded memory technology evolves, the traditional Static Random Access Memory (SRAM) technology has reached the end of development. For deepening the manufacturing process technology, the next generation memory technology is highly required because of the exponentially increasing leakage current of SRAM. Non-volatile memories such as STT-MRAM (Spin Torque Transfer Magnetic Random Access Memory), PCM (Phase Change Memory) are good candidates for replacing SRAM technology in embedded memory systems. They have many advanced characteristics in the perspective of power consumption, leakage power, size (density) and latency. Nonetheless, nonvolatile memories have two major problems that hinder their use it the next-generation memory. First, the lifetime of the nonvolatile memory cell is limited by the number of write operations. Next, the write operation consumes more latency and power than the same size of the read operation.These disadvantages can be solved using the compiler. The disadvantage of non-volatile memory is in write operations. Therefore, when the compiler decides the layout of the data, it is solved by optimizing the write operation to allocate a lot of data to the SRAM. This study provides insights into how these compiler and architectural designs can be developed.

• International Journal of Internet, Broadcasting and Communication
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• 제9권1호
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• pp.29-34
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• 2017

Over the past several decades, embedded system and flight control computer technologies have been evolved to meet the diverse needs of the mobile device market. Current embedded systems are at the heart of technologies that can take advantage of small-sized specialized hardware while still providing high-efficiency performance at low cost. One of these key technologies is multiple memory banks. For example, a dual memory bank can provide two times more memory bandwidth in the same memory space. This benefit take lower cost to provide the same bandwidth. However, there is still few software technologies to support the efficient use of multiple memory banks. In this study, we present a technique to efficiently exploit multiple memory banks by software support. Specifically, our technique use an interference graph to optimally allocate data to different memory banks by an optimizing compiler. As a result, the execution time can be improved upto 7% with the proposed technique.

• JSTS:Journal of Semiconductor Technology and Science
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• 제2권2호
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• pp.111-124
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• 2002

The ferroelectric RAM (FeRAM) has a great advantage for a system on a chip (SOC) and mobile product memory, since FeRAM not only supports non-volatility but also delivers a fast memory access similar to that of DRAM and SRAM. This work develops at three levels: 1) low voltage operation with boost voltage control of bitline and plateline, 2) reducing bitline capacitance with multiple divided sub cell array, and 3) increasing chip performance with write operation sharing both active and precharge time period. The key techniques are implemented on the proposed hierarchy bitline scheme with proposed hybrid-bitline and high voltage boost control. The test chip and simulation results show the performance of sub-1.5 voltage operation with single step pumping voltage and self-boost control in a cell array block of 1024 ($64{\;}{\times}{\;}16$) rows and 64 columns.

• 대한전자공학회논문지SD
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• 제42권2호
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• pp.49-56
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• 2005

본 논문에서는 사용자로부터 테스트하고자 하는 고장 모델을 입력받아 적절한 much 테스트 알고리즘을 만들고 BIST 회로를 생성해 주는 Memory BIST Circuit Creation System(MBCCS) 을 제안하고 있다. 기존의 툴들은 널리 사용되고 있는 알고리즘에 국한되어 메모리의 사양이 변할 경우 거기에 맞는 BIST 회로를 다시 생성해주는 번거로움이 있었다. 하지만 본 논문에서 제안한 툴에서는 다양해진 메모리 구조에 적합한 메모리 BIST 회로를 사용자 요구에 맞는 알고리즘을 적용해서 자동적으로 생성하게 하였고, 임의적으로 선택된 고장 모델에 대한 알고리즘을 제안된 규칙에 따라 최적화함으로 해서 효율성을 높였다. 또한 다양한 크기의 폭을 갖는 주소와 데이터를 지원하며 IEEE 1149.1 회로와의 인터페이스도 고려하였다.

• Journal of Computing Science and Engineering
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• 제3권3호
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• pp.181-194
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• 2009

Flash memory is increasingly being used in a wide range of storage applications because of its low power consumption, low access latency, small form factor, and high shock resistance. However, the current platforms for flash memory software development do not meet the ever-increasing requirements of flash memory applications. This paper presents three different hardware platforms for flash memory/NVRAM (non-volatile RAM) software development that overcome the limitations of the current platforms. The three platforms target different types of host system and provide various features that facilitate the development and verification of flash memory/NVRAM software. In this paper, we also demonstrate the usefulness of the three platforms by implementing three different types of storage system (one for each platform) based on them.

• Journal of Information Processing Systems
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• 제16권3호
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• pp.588-598
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• 2020

An alternative state estimation filtering algorithm is designed for continuous time systems with noises as well as control input. Two kinds of estimation filters, which have different measurement memory structures, are operated selectively in order to use both filters effectively as needed. Firstly, the estimation filter with infinite memory structure is operated for a certain continuous time system. Secondly, the estimation filter with finite memory structure is operated for temporarily uncertain continuous time system. That is, depending on the presence of uncertainty, one of infinite memory structure and finite memory structure filtered estimates is operated selectively to obtain the valid estimate. A couple of test variables and declaration rule are developed to detect uncertainty presence or uncertainty absence, to operate the suitable one from two kinds of filtered estimates, and to obtain ultimately the valid filtered estimate. Through computer simulations for a continuous time aircraft engine system with different measurement memory lengths and temporary model uncertainties, the proposed state estimation filtering algorithm can work well in temporarily uncertain as well as certain continuous time systems. Moreover, the proposed state estimation filtering algorithm shows remarkable superiority to the infinite memory structure filtering when temporary uncertainties occur in succession.

• International journal of advanced smart convergence
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• 제1권2호
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• pp.26-29
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• 2012

Recently, to efficiently support the real-time requirements of RTLS( Real Time Location System) services, interest in the main memory DBMS is rising. In the main memory DBMS, because all data can be lost when the system failure happens, the recovery method is very important for the stability of the database. Especially, disk I/O in executing the log and the checkpoint becomes the bottleneck of letting down the total system performance. Therefore, it is urgently necessary to research about the recovery method to reduce disk I/O in the main memory DBMS. Therefore, In this paper, we analyzed existing log techniques and check point techniques and existing main memory DBMSs' recovery techniques for recovery techniques research for main memory DBMS.

• 반도체디스플레이기술학회지
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• 제9권2호
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• pp.67-72
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• 2010

Recently increasing application of flash memory in mobile and ubiquitous related devices is due to its non-volatility, fast response time, shock resistance and low power consumption. Following this trend, SSD(Solid State Disk) using multiple flash chips, instead of hard-drive based storage system, started to widely used for its advantageous features. However, flash memory based storage subsystem should resolve the performance bottleneck for writing in perspective of speed and lifetime according to its disadvantageous physical property. In order to provide tangible performance, solutions are studied in aspect of reclaiming of invalid regions by decreasing the number of erasures and distributing the erasures uniformly over the whole memory space as much as possible. In this paper, we study flash memory recycling algorithms with multiple management units and demonstrate that the proposed algorithm provides feasible performance. The proposed method utilizes the partitions of the memory space by utilizing threshold values and reconfigures the management units if necessary. The performance of the proposed policies is evaluated through a number of simulation based experiments.

• 정보처리학회논문지A
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• 제11A권3호
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• pp.157-162
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• 2004

본 논문에서는 가상 메모리 압축 알고리즘으로 CAMD 알고리즘을 제안한다. CAMD 알고리즘은 페이지 폴트가 일어났을 때 이들 페이지들을 스왑 디바이스로 이동시키지 않고 주기억장치 내의 압축된 캐시 영역을 할당하여 압축된 페이지를 저장한다. 이렇게 함으로써 스왑 디바이스로 이동하는 시간과 횟수를 감소시켜서 페이지 폴트 응답시간을 줄이며 주기억장치에 저장되는 페이지들의 공간 활용도를 높일 수 있다. 메모리 내의 데이터는 일반적인 압축 알고리즘에서 다루는 데이터와는 다른 특징들을 가지고 있어서 메모리 내의 주소 값이나 배열 데이터와 값은 요소들을 고려하여 압축될 때의 효율성을 높일 수 있다.