• IEMEK Journal of Embedded Systems and Applications
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• v.13 no.5
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• pp.261-268
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• 2018

Phase Change Memory(PCM) with low power consumption and high integration attracts attention as a next generation nonvolatile memory replacing DRAM. However, there is a problem that PCM has long latency and high energy consumption due to the writing operation. The PCM & DRAM hybrid memory structure is a fruitful structure that can overcome the disadvantages of such PCM. However, the page replacement algorithm is important, because these structures use two memory of different characteristics. The purpose of this document is to effectively manage pages that can be referenced in memory, taking into account the characteristics of DRAM and PCM. In order to manage these pages, this paper proposes an page replacement algorithm based on frequently accessed and recently paged. According to our simulation, the proposed algorithm for the DRAM&PCM hybrid can reduce the energy-delay product by around 10%, compared with Clock-DWF and CLOCK-HM.

• Proceedings of the KSR Conference
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• 2010.06a
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• pp.1068-1074
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• 2010

In high speed railway, event recorder is essential system for analyzing the cause of train accident. It stores train operation sent by train control system in safe memory unit. Crash protected memory, the safe memory unit for event recorder, keeps the stored contents from severe environment. For crash protected memory, we have designed the architecture of concrete enclosure and controller board. Proposed system provides large volume of memory capacity and fault tolerance architecture. For checking the characteristics of proposed crash protected memory specification, the simulation is executed. Simulation results shows the designed crash protected memory meets all requirements.

• Journal of the Semiconductor & Display Technology
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• v.19 no.3
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• pp.112-117
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• 2020

NAND flash memory is a non-volatile memory that retains stored data even without power supply. Internal memory used as a data storage device and solid-state drive (SSD) is used in portable devices such as smartphones and digital cameras. However, NAND flash memory carries the risk of electric shock, which can cause errors during read/write operations, so use error correction codes to ensure reliability. It efficiently recovers bad block information, which is a defect in NAND flash memory. BBT (Bad Block Table) is configured to manage data to increase stability, and as a result of experimenting with the error correction code algorithm, the bit error rate per page unit of 4Mbytes memory was on average 0ppm, and 100ppm without error correction code. Through the error correction code algorithm, data stability and reliability can be improved.

• Journal of Korea Multimedia Society
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• v.24 no.7
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• pp.922-932
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• 2021

This thesis mainly studies the impact of short-term memory in VR tour games on users. The thesis is based on VR tour games and short-term memory, using the literature research method, the practical research method, and the investigation method. First, the author designs and makes VR tour games on the Beijing-Hangzhou Grand Canal, and then conducts a questionnaire survey and designs a control experiment. The experiment explores the differences of the short-term memory level of individuals between the normal environment and the VR tour game environment. It verifies whether the influential hypothesis proposed by the research is correct. Research conclusions show that: VR tour games have an impact on short-term memory. Compared with the normal environment, the subjects have better performance in the VR tour game mode and can maintain a high short-term memory level for a longer time. Its conclusions should promote the cultural propaganda of scenic spots and provide theoretical support for tourists' short-term memory of scenic spots culture.

• Journal of the Semiconductor & Display Technology
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• v.21 no.1
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• pp.85-90
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• 2022

In this paper, an asynchronous nonvolatile memory module using a self-diagnosis function was designed. For the system to work, a lot of data must be input/output, and memory that can be stored is required. The volatile memory is fast, but data is erased without power, and the nonvolatile memory is slow, but data can be stored semi-permanently without power. The non-volatile static random-access memory is designed to solve these memory problems. However, the non-volatile static random-access memory is weak external noise or electrical shock, data can be some error. To solve these data errors, self-diagnosis algorithms were applied to non-volatile static random-access memory using error correction code, cyclic redundancy check 32 and data check sum to increase the reliability and accuracy of data retention. In addition, the possibility of application to an asynchronous non-volatile storage system requiring reliability was suggested.

• Proceedings of the Korean Institute of Information and Commucation Sciences Conference
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• 2011.05a
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• pp.436-439
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• 2011

As mobile digital devices have come into more widespread use, the demand for mobile storage devices have been increasing rapidly and most of digital cameras and camcorders are using SD memory cards. The SD memory card are generally employing a form of copying data into a personal computer after storing user data based on flash memory. The current paper proposes the SD memory card of being capable of storing photograph and image data through network rather than using a method of storing data in flash memory. By delivering data and memory address values obtained through SD Slave IP to network server without sending them to flash memory, one can store data necessary to be stored in a computer's SD memory in real time in a safe and convenient way.

• ETRI Journal
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• v.44 no.3
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• pp.450-461
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• 2022

The Gen-Z protocol is a memory semantic protocol between the memory and CPU used in computer architectures with large memory pools. This study presents the implementation of the Gen-Z hardware system configured using Gen-Z specification 1.0 and reports its performance. A hardware prototype of a DDR4 Gen-Z memory pool with an optimized character, a block device driver, and a file system for the Gen-Z hardware was designed. The Gen-Z IP was targeted to the FPGA, and a 512 GB Gen-Z memory pool was configured on an ×86 server. In the experiments, the latency and throughput of the Gen-Z memory were measured and compared with those of the local memory, SATA SSD, and NVMe using character or block device interfaces. The Gen-Z hardware exhibited superior throughput and latency performance compared with SATA SSD and NVMe at block sizes under 4 kB. The MySQL and File IO benchmark of Gen-Z showed good write performance in all block sizes and threads. Besides, it showed low latency in RocksDB's fillseq dbbench using the ext4 direct access filesystem.

• ETRI Journal
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• v.44 no.6
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• pp.1020-1033
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• 2022

In this paper, we propose novel disaggregated memory module (dMM) architecture and memory access control schemes to solve the collision and contention problems of memory disaggregation, reducing the average memory access time to less than 1 ㎲. In the schemes, the distributed scheduler in each dMM determines the order of memory read/write access based on delay-sensitive priority requests in the disaggregated memory access frame (dMAF). We used the memory-intensive first (MIF) algorithm and priority-based MIF (p-MIF) algorithm that prioritize delay-sensitive and/or memory-intensive (MI) traffic over CPU-intensive (CI) traffic. We evaluated the performance of the proposed schemes through simulation using OPNET and hardware implementation. Our results showed that when the offered load was below 0.7 and the payload of dMAF was 256 bytes, the average round trip time (RTT) was the lowest, ~0.676 ㎲. The dMM scheduling algorithms, MIF and p-MIF, achieved delay less than 1 ㎲ for all MI traffic with less than 10% of transmission overhead.

• BMB Reports
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• v.52 no.2
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• pp.127-132
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• 2019

Cells must fine-tune their gene expression programs for optimal cellular activities in their natural growth conditions. Transcriptional memory, a unique transcriptional response, plays a pivotal role in faster reactivation of genes upon environmental changes, and is facilitated if genes were previously in an active state. Hyper-activation of gene expression by transcriptional memory is critical for cellular differentiation, development, and adaptation. TREM (Transcriptional REpression Memory), a distinct type of transcriptional memory, promoting hyper-repression of unnecessary genes, upon environmental changes has been recently reported. These two transcriptional responses may optimize specific gene expression patterns, in rapidly changing environments. Emerging evidence suggests that they are also critical for immune responses. In addition to memory B and T cells, innate immune cells are transcriptionally hyperactivated by restimulation, with the same or different pathogens known as trained immunity. In this review, we briefly summarize recent progress in chromatin-based regulation of transcriptional memory, and its potential role in immune responses.

• The Journal of Korean Association of Computer Education
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• v.15 no.3
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• pp.37-47
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• 2012

One of the major goals in high school Informatics is for students to develop creative problem-solving abilities based on knowledge on computer science. Thus, the contents of the textbooks should be accurate and appropriate. However, we discovered that the current Informatics textbooks contain the untrue and/or inappropriate descriptions of main memory and virtual memory. The textbooks describe that main memory is composed of RAM and ROM. The virtual memory is described as a technique in which a part of the secondary storage is utilized as main memory to execute an application of which size is larger than that of main memory. In this study, we attempted to uncover the root causes of the fallacies, and suggest the accurate explanations by comparing with renowned books adopted in most schools worldwide including USA. Our study reveals that it is inappropriate to include ROM in main memory from the memory hierarchy perspective. Virtual memory is a technique that provides convenience to programmers, through which an operating system loads the necessary portion of a program from secondary storage to main memory. As for the advantages of virtual memory in the current computer systems, the focus should be on providing the effective multitasking capability, rather than on executing a larger program than the size of main memory. We suggest that it is appropriate to exclude virtual memory in textbooks considering its complexity.