Performance Improvement of Asynchronous Mass Memory Module Using Error Correction Code

에러 보정 코드를 이용한 비동기용 대용량 메모리 모듈의 성능 향상

  • Ahn, Jae Hyun (Semiconductor Engineering of Cheongju University) ;
  • Yang, Oh (Semiconductor Engineering of Cheongju University) ;
  • Yeon, Jun Sang (WOOJIN Industrial System Co. Ltd.)
  • 안재현 (청주대학교 반도체공학과) ;
  • 양오 (청주대학교 반도체공학과) ;
  • 연준상 (우진산전(주))
  • Received : 2020.09.17
  • Accepted : 2020.09.23
  • Published : 2020.09.30

Abstract

NAND flash memory is a non-volatile memory that retains stored data even without power supply. Internal memory used as a data storage device and solid-state drive (SSD) is used in portable devices such as smartphones and digital cameras. However, NAND flash memory carries the risk of electric shock, which can cause errors during read/write operations, so use error correction codes to ensure reliability. It efficiently recovers bad block information, which is a defect in NAND flash memory. BBT (Bad Block Table) is configured to manage data to increase stability, and as a result of experimenting with the error correction code algorithm, the bit error rate per page unit of 4Mbytes memory was on average 0ppm, and 100ppm without error correction code. Through the error correction code algorithm, data stability and reliability can be improved.

Keywords

References

  1. Jungwon Kim, Seungkyun Kim, Jeajin Lee, Changhee Jung, Duk-Kyun Woo, "Memory Hierarchy Optimization in Embedded Systems using On-Chip SRAM", Journal of KIISE: Computer Systems and Theory 36(2), pp. 102-110, 2009.4.
  2. Myeong Kyun Kim, Oh Yang, Won Sup Chung, "Implementation of the FAT32 File System using PLC and CF Memory", Journal of the Semiconductor & Display Technology, Vol. 11, No. 2. June 2012.
  3. Lee Ki-jun, Lee Myung-Kyu, Shin Bum-kyu, Gong Joon-jin, "NAND flash memory storage device Error control code application", The Journal of The Korean Institute of Communication Sciences 32(6), pp. 16-22, 2015.05.
  4. Dong-Hwan Lee, Kwang-Hee Phark, Shao-hu Peng, Deok-Hwan Kim, "IRAW ECC for ensuring ECC Integrity of Flash memory", The Journal of The Korean Institute of Communication Sciences 35(2B), pp. 451-454, 2008.10.
  5. Jisu Kwon, Daejin Park, "Acceleration of ECC Computation for Robust Massive Data Reception under GPU-based Embedded Systems", Journal of the Korea Institute of Information and Communication Engineering 24(7), pp. 956-962, 2020.7.
  6. Jae-bin Lee, Geon-Myung Kim, Yi-Hyun Park, Seung-Ho Lim, "NAND Flash Memory Storage with Rate-Compatible LDPC", Journal of Academic Presentation of the Korean Society of Information Sciences, pp. 1519-1521, 2019.06.
  7. Yongju Song, Young Ik Eom, "Analysis of Hot/Cold Data Separation Scheme for Data Retention Error on NAND Flash Memory", Journal of Academic Presentation of the Korean Society of Information Sciences, pp. 1395-1397, 2017.06.
  8. Seong Ryeol Kim, "The Proposed of the Encryption Method and Designed of the Secure Key Using Initial Bad Block Information Physical Address of NAND Flash Memory", Journal of the Korea Institute of Information and Communication Engineering 20(12), pp. 2282-2288, 2016.12. https://doi.org/10.6109/jkiice.2016.20.12.2282
  9. Hongseok Kim, Ki Jun Kim, Sang Lyul Min, "Fast address translation of bad block management scheme in flash memory storage devices using bloom filters", Journal of Academic Presentation of the Korean Society of Information Sciences, pp. 1053-1055, 2014.12.
  10. Hongseok Kim, Eyee Hyun Nam, "Design and implementation of bad block management layer for high performance flash memory-based storage devices", Journal of Academic Presentation of the Korean Society of Information Sciences 39(2A), pp. 90-92, 2012.11.
  11. Stefano Gregori, Alessandro Cabrini, Osama Khouri, Guido Torelli, "On-chip error correction techniques for new-generation flash memories," Proc. of IEEE, Vol.91, No.4, pp. 602-616, 2003. https://doi.org/10.1109/JPROC.2003.811709
  12. Wei Liu, Junrye Rho, Wonyong Sung, "Low-power high-throughput BCH error correction VLSI design for multi-level cell NAND flash memories," IEEE Workshop on Signal Processing Systems (SIPS), pp. 248-253, 2006.
  13. Namgi Kim, "Variable CRC Scheme for Efficient Data Transmission Control for IEEE 802.16e Wireless Network", The Journal of Korean Institute of Information Technology 7(3), pp. 109-115, 2009.6.
  14. Oh Yang, Seungkyu Ock, "The Design of Multi-channel Synchronous Communication IC Using FPGA", Journal of the Semiconductor & Display Technology, Vol. 10, No. 3. September 2011.