• 한국컴퓨터정보학회논문지
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• 제24권7호
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• pp.1-8
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• 2019

Recently, an SSD with hybrid buffer memories is actively researching to reduce the overall latency in server computing systems. However, existing hybrid buffer policies caused many swapping operations in pages because it did not consider the overall latency such as read/write operations of flash chips in the SSD. This paper proposes the clock with hybrid buffer memories (CLOCK-HBM) for a new hybrid buffer policy in the SSD with server computing systems. The CLOCK-HBM constructs new policies based on unique characteristics in both DRAM buffer and NVMs buffer for reducing the number of swapping operations in the SSD. In experimental results, the CLOCK-HBM reduced the number of swapping operations in the SSD by 43.5% on average, compared with LRU, CLOCK, and CLOCK-DNV.

• ETRI Journal
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• 제36권6호
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• pp.988-998
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• 2014

For memory-based big data storage, using hybrid memories consisting of both dynamic random-access memory (DRAM) and non-volatile random-access memories (NVRAMs) is a promising approach. DRAM supports low access time but consumes much energy, whereas NVRAMs have high access time but do not need energy to retain data. In this paper, we propose a new data migration method that can dynamically move data pages into the most appropriate memories to exploit their strengths and alleviate their weaknesses. We predict the access frequency values of the data pages and then measure comprehensively the gains and costs of each placement choice based on these predicted values. Next, we compute the potential benefits of all choices for each candidate page to make page migration decisions. Extensive experiments show that our method improves over the existing ones the access response time by as much as a factor of four, with similar rates of energy consumption.

• 반도체디스플레이기술학회지
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• 제20권4호
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• pp.10-15
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• 2021

Cache bypassing schemes have been studied to remove unnecessary updating the data in cache blocks. Among them, a statistics-based cache bypassing method for asymmetric-access caches is one of the most efficient approach for non-voliatile memories and shows the lowest cache access latency. However, it is proposed under the condition of the normal cache system, so further study is required for the hybrid cache architecture. This paper proposes a novel cache bypassing scheme, called hybrid bypassing block selector. In the proposal, the new model is established considering the SRAM region and the non-volatile memory region separately. Based on the model, hybrid bypassing decision block is implemented. Experiments show that the hybrid bypassing decision block saves overall energy consumption by 21.5%.

• 한국컴퓨터정보학회논문지
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• 제24권8호
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• pp.1-8
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• 2019

Modern computers provide tremendous computing capability and a large memory system. Hybrid memories consist of next generation memory devices and are adopted in high performance systems. However, the increased complexity of the microprocessor makes it difficult to operate the system effectively. In this paper, we propose a simple data migration method called Bandwidth-aware Data Migration (BDM) to efficiently use memory systems for high performance processors with hybrid memory. BDM monitors the status of applications running on the system using hardware performance monitoring tools and migrates the appropriate pages of selected applications to High Bandwidth Memory (HBM). BDM selects applications whose bandwidth usages are high and also evenly distributed among the threads. Experimental results show that BDM improves execution time by an average of 20% over baseline execution.

• 한국전자통신학회논문지
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• 제11권6호
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• pp.611-618
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• 2016

제안한 논문은 통신 네트워크 및 관련 시스템 기술에 관한 연구로 USB메모리와 클라우드 스토리지 영역을 동시에 동기화하여 네트워크 오류에 따른 클라우드 스토리지 영역 사용부재 또는 USB 메모리를 분실하는 상황이 발생되더라도 데이터를 안전하게 유지관리하기 위한 기술설계이다. 클라우드를 활용하는 사용자들의 안전한 문서관리 정책의 필요성을 기반으로 매체의 분실 및 네트워크의 오류에 따른 대책을 하이브리드형 클라우드 시스템으로 설계구축하고, 사용자의 편리성에 따른 자동 및 수동 동기화 방법을 설계한다. 마지막으로 윈도우즈 환경에 적합한 사용자의 편의보장을 위해 탐색기형 스토리지 UI를 설계함으로써 점차 늘어나는 클라우드 사용자의 안전성과 편리성을 모두 보장해주기 위한 시스템설계이다.

• 반도체디스플레이기술학회지
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• 제23권1호
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• pp.65-70
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• 2024

Direct cache-to-cache transfer has been studied to reduce the latency and bandwidth consumption related to the shared data in multiprocessor system. Even though these studies lead to meaningful results, they assume that caches consist of SRAM. For example, if the system employs the non-volatile memory, the one of the most important parts to consider is to decrease the number of write operations. This paper proposes a hybrid write avoidance cache coherence protocol that considers the hybrid cache architecture. A new state is added to finely control what is stored in the non-volatile memory area, and experimental results showed that the number of writes was reduced by about 36% compared to the existing schemes.

• 한국표면공학회지
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• 제51권6호
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• pp.387-392
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• 2018

Nanopatterning is one of the essential nanotechnologies to fabricate electronic and energy nanodevices. Therefore, many research group members made a lot of efforts to develop simple and useful nanopatterning methods to obtain highly ordered nanostructures with functionality. In this study, in order to achieve pattern formation of three-dimensional (3D) hierarchical nanostructures, we introduce a simple and useful patterning method (nano-transfer printing (n-TP) process) consisting of various linewidths for diverse materials. Pt and $WO_3$ hybrid line structures were successfully stacked on a flexible polyimide substrate as a multi-layered hybrid 3D pattern of Pt/WO3/Pt with line-widths of $1{\mu}m$, $1{\mu}m$ and 250 nm, respectively. This simple approach suggests how to fabricate multiscale hybrid nanostructures composed of multiple materials. In addition, functional hybrid nanostructures can be expected to be applicable to various next-generation electronic devices, such as nonvolatile memories and energy harvesters.

• 대한전자공학회:학술대회논문집
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• 대한전자공학회 2009년도 정보 및 제어 심포지움 논문집
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• pp.240-242
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• 2009

Flash memories are one of best media to support future computer's storages. However, we need to improve traditional data management scheme due to the relatively slow characteristics of flash operation of SSD. Due to the unique characteristics of flash media and hard disk, the efficiency of I/O processing is severely reduced without special treatment, especially in the presence of heavy workload or bulk data copy. In this respect, we need to design and develop efficient hybrid-RAID storage system.

• 대한임베디드공학회논문지
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• 제12권3호
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• pp.169-176
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• 2017

To replace conventional DRAM, many researches have been done on nonvolatile memories. The DRAM&PCM hybrid memory is one of the effective structure because it can utilize an advantage of DRAM and PCM. However, in order to use this characteristics, pages can be replaced frequently between DRAM and PCM. Therefore, PCM still has major problem that has write-limits. Therefore, it needs an effective page management method for exploiting each memory characteristics dynamically and adaptively. So we aim reducing an average access time and write count of PCM by utilizing two locality for an effective page replacement. We proposed a page selection algorithm which is recently requested to write in DRAM and an algorithm witch uses two locality in PCM. According to our simulation, the proposed algorithm for the DRAM&PCM hybrid can reduce the PCM write count by around 22% and the average access time by 31% given the same PCM size, compared with CLOCK-DWF algorithm.

• 대한임베디드공학회논문지
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• 제11권4호
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• pp.201-208
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• 2016

Non-volatile counter is a counter that maintains the value without external power supply. It has been used for the applications related to warranty issues to count and record certain events such as power cycles, operating time, hard resets, and timeouts. It has been conventionally implemented with volatile memory-based counter and battery backup or non-volatile memory such as EEPROM. Both of them have a lifetime issue due to the limited lifetime of the battery and the endurance of the non-volatile memory cells, which incurs significant redundancy in design. In this paper, we introduce a hybrid architecture of volatile (SRAM) and non-volatile memory (EEPROM) cells to achieve required lifetime of the non-volatile counter with smaller cost. We conduct a design space exploration of the proposed hybrid architecture with the parameters of various kinds of non-volatile memories. The analysis result shows that the proposed hybrid non-volatile counter can extend the lifetime up to 6 times compared to the battery-backup volatile memory-based implementation.