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Low Power Scheme Using Bypassing Technique for Hybrid Cache Architecture  

Choi, Juhee (Dept. of Smart Information Communication Engineering, Sangmyung University)
Publication Information
Journal of the Semiconductor & Display Technology / v.20, no.4, 2021 , pp. 10-15 More about this Journal
Abstract
Cache bypassing schemes have been studied to remove unnecessary updating the data in cache blocks. Among them, a statistics-based cache bypassing method for asymmetric-access caches is one of the most efficient approach for non-voliatile memories and shows the lowest cache access latency. However, it is proposed under the condition of the normal cache system, so further study is required for the hybrid cache architecture. This paper proposes a novel cache bypassing scheme, called hybrid bypassing block selector. In the proposal, the new model is established considering the SRAM region and the non-volatile memory region separately. Based on the model, hybrid bypassing decision block is implemented. Experiments show that the hybrid bypassing decision block saves overall energy consumption by 21.5%.
Keywords
Bypass Algorithm; Non-Volatile Memories; Hybrid Cache Architecture; Low Power;
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1 J. Sung, J. Jeong, and G. Lee, "Reliability Analysis by Lateral Charge Migration in Charge Trapping Layer of SONOS NAND Flash Memory Devices," Journal of the Semiconductor & Display Technology, vol. 18, no. 4, pp. 138-142, 2019.
2 S. Yoon, and J. Nah, "Hybrid Memory Adaptor for OpenStack Swift Object Storage," Journal of the Semiconductor & Display Technology, vol. 19, no. 3, pp. 61-67, 2020.
3 S. Rodriguez and B. Jacob. "Energy/power breakdown of pipelined nanometer caches (90nm/65nm/45nm/32nm)," In Proceedings of the 2006 international symposium on Low power electronics and design, pp. 25-30. 2006.
4 H. Dybdahl and P. Stenstrom. "Enhancing last-level cache performance by block bypassing and early miss determination," In Asia-Pacific Conference on Advances in Computer Systems Architecture, pp. 52-66, 2006.
5 J. Li, L. Shi, C. J. Xue, C. Yang, and Y. Xu, "Exploiting set-level write non-uniformity for energy-efficient nvm-based hybrid cache," in Embedded Systems for Real-Time Multimedia (ESTIMedia), IEEE Symposium on, pp. 19-28, 2011.
6 J. Gaur, M. Chaudhuri, and S. Subramoney. "Bypass and insertion algorithms for exclusive last-level caches," ACM SIGARCH Computer Architecture News, no. 39, pp. 81-92, 2011.   DOI
7 M. Kharbutli and D. Solihin. "Counter-based cache replacement and bypassing algorithms," Computers, IEEE Transactions on, no. 57, pp. 433-447, 2008.
8 C. Zhang, G. Sun, P. Li, T. Wang, D. Niu, and Y. Chen. "Sbac: a statistics based cache bypassing method for asymmetric-access caches," In Proceedings of the international symposium on Low power electronics and design, pp. 345-350, 2014.
9 Z. Diao, Z. Li, S. Wang, Y. Ding, A. Panchula, E. Chen, L.-C. Wang, and Y. Huai. "Spin-transfer torque switching in magnetic tunnel junctions and spin-transfer torque random access memory," Journal of Physics: Condensed Matter, no. 16, pp. 165209, 2007.
10 Z. Wang, D. A. Jimenez, C. Xu, G. Sun, and Y. Xie, "Adaptive placement and migration policy for an stt-ram-based hybrid cache," in High Performance Computer Architecture (HPCA), IEEE International Symposium on, pp. 13-24, 2014.
11 J. Power, J. Hestness, M. S. Orr, M. D. Hill, and D. A. Wood, "gem5-gpu: A heterogeneous cpu-gpu simulator," IEEE Computer Architecture Letters, vol. 14, no. 1, pp. 34-36, 2015.   DOI
12 T. Kim, O. Yang, and J. Yeon, "Design of Asynchronous Non-Volatile Memory Module Using NAND Flash Memory and PSRAM," Journal of the Semiconductor & Display Technology, vol. 19, no. 5, pp. 118-123, 2020.
13 S. Gupta, H. Gao, and H. Zhou. "Adaptive cache bypassing for inclusive last level caches." In Parallel & Distributed Processing (IPDPS), IEEE International Symposium on, pp. 1243-1253, 2013.
14 B. Quan, T. Zhang, T. Chen, and J. Wu, "Prediction table based management policy for stt-ram and sram hybrid cache," in Computing and Convergence Technology (ICCCT), IEEE International Conference on, pp. 1092-1097, 2012.
15 J. Henning, "Spec cpu2006 benchmark descriptions," SIGARCH Comput. Archit. News, vol. 34, no. 4, p. 1-17, 2006.   DOI
16 Xu, Y., Xu, Y., Tang, M., Zhang, L., and Lan, Y. "Asymmetry & Locality-Aware Cache Bypass and Flush for NVM-Based Unified Persistent Memory," In 2019 IEEE Intl Conf on Parallel & Distributed Processing with Applications, Big Data & Cloud Computing, Sustainable Computing & Communications, Social Computing & Networking (ISPA/BDCloud/SocialCom/SustainCom), pp. 168-175, 2019.
17 X. Dong, C. Xu, Y. Xie, and N. P. Jouppi, "Nvsim: A circuit-level performance, energy, and area model for emerging nonvolatile memory," IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems, vol. 31, no. 7, pp. 994-1007, 2012.   DOI