• Journal of the Korean Institute of Electrical and Electronic Material Engineers
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• v.31 no.2
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• pp.74-79
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• 2018

In this report, the results of a systematic study on the effects of polycrystalline silicon gate depletion on the reliability characteristics of metal-oxide semiconductor field-effect transistor (MOSFET) devices were discussed. The devices were fabricated using standard complimentary metal-oxide semiconductor (CMOS) processes, wherein phosphorus ion implantation with implant doses varying from $10^{13}$ to $5{\times}10^{15}cm^{-2}$ was performed to dope the polycrystalline silicon gate layer. For implant doses of $10^{14}/cm^2$ or less, the threshold voltage was increased with the formation of a depletion layer in the polycrystalline silicon gate layer. The gate-depletion effect was more pronounced for shorter channel lengths, like the narrow-width effect, which indicated that the gate-depletion effect could be used to solve the short-channel effect. In addition, the hot-carrier effects were significantly reduced for implant doses of $10^{14}/cm^2$ or less, which was attributed to the decreased gate current under the gate-depletion effects.

• Proceedings of the KIEE Conference
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• 2009.07a
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• pp.1238_1239
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• 2009

본 논문에서는 ELA poly-Si TFT보다 뛰어난 균일도를 갖고, a-Si:H TFT보다 전기적 안정도가 우수한 PMOS SPC-Si TFT의 특성을 연구하였다. SPC-Si의 계면 특성을 향상 시키기 위해 $SiO_2$ 게이트 절연막을 증착하기 전에 Solid Phase Crystalline 실리콘(SPC-Si) 채널 영역에 다양한 H2 플라즈마 처리를 해주었다. PECVD를 이용하여 100W에서 H2 플라즈마 처리를 5분 해주었을 때 SPC-Si TFT의 전기적 특성이 향상되는 것을 볼 수 있는데, $V_{TH}$가 약 -3.91V, field effect mobility가 $22.68cm^2$/Vs, 그리고 Subthreshold swing이 0.64 정도를 보였다. 또한 소자에 Hot carrier stress($V_{GS}$=14.91V, $V_{DS}$=-15V, for 2,000sec)를 주었을 때도 전기적 특성이 변하지 않았으며, 일정한 bias stress($V_{GS}$=-15V, $V_{DS}$=-10V, for 2,000sec)를 가하였을 때도 $V_{TH}$가 증가하지 않았다. 이러한 결과를 통해 SPC-Si가 poly-Si TFT보다 더욱 안정함을 알 수 있었다.

• The Transactions of The Korean Institute of Electrical Engineers
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• v.56 no.4
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• pp.705-715
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• 2007

Recently, the interest on power quality has been hot issue because the equipments cause voltage disturbance and have become more sensitive to the voltage disturbance. Additionally, the reseach on power electronic equipments applying to the high power has been increased. This paper deals with Line-Interactive Dynamic Voltage Restorer(LIDVR) system using 7-Level H-Bridge inverter, which is one of the solutions to compensate the voltage disturbance and to increase the power of equipments. The LIDVR has the following advantages comparing to the DVR with the series injection transformer. It has the power factor near to unity under the condition of normal source voltage, can compensate the harmonic current of the load and the instant interruption, and has the fast response. First, the construction, the operation mode and algebraic modeling of LIDVR are reviewed. And then the voltage control algorithm is proposed to get the sinusoidal load voltage with constant amplitude. Finally, simulation and experiment results verify the proposed LIDVR system.

• Journal of Information Technology Applications and Management
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• v.15 no.1
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• pp.261-270
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• 2008

Wireless Mesh Networks (WMNs) have emerged as one of the new hot topics in wireless communications. WMNs have been suggested for use in situations in which some or all of the users are mobile or are located in inaccessible environments. Unconstrained transmission in a WMN may lead to the time overlap of two or more packet receptions, called collisions or interferences, resulting in damaged useless packets at the destination. There are two types of collisions; primary collision, due to the transmission of the stations which can hear each other, and hidden terminal collision, when stations outside the hearing range of each other transmit to the same receiving stations. For a WMN, direct collisions can be minimized by short propagation and carrier sense times. Thus, in this paper we only consider hidden terminal collision while neglecting direct collisions. To reduce or eliminate hidden terminal collision, code division multiple access (CDMA) protocols have been introduced. The collision-free property is guaranteed by the use of spread spectrum communication techniques and the proper assignment of orthogonal codes. Such codes share the fixed channel capacity allocated to the network in the design stage. Thus, it is very important to minimize the number of codes while achieving a proper transmission quality level in CDMA WMNs. In this paper, an efficient heuristic code assignment algorithm for eliminating hidden terminal collision in CDMA WMNs with general topology.

• Proceedings of the Korean Institute of Electrical and Electronic Material Engineers Conference
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• 2004.11a
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• pp.239-242
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• 2004

A stoichiometric mixture of evaporating materials for $CdIn_2S_4$ single crystal thin films was prepared from horizontal furnace. To obtain the single crystal thin films, $CdIn_2S_4$ mixed crystal was deposited on thoroughly etched semi-insulating GaAs(100) substrate by hot wall epitaxy(HWE) system. The source and substrate temperatures were $630^{\circ}C$ and $420^{\circ}C$ respectively. The crystalline structure of single crystal thin films was investigated by the photoluminescence and double crystal X-ray diffraction(DCXD). The carrier density and mobility of $CdIn_2S_4$ single crystal thin films measured from Hall effect by van der Pauw method are $9.01{\times}10^{16}\;cm^{-3}$ and $219\;cm^2/V{\cdot}s$ at 293 K, respectively. From the optical absorption measurement, the temperature dependence of energy band gap on $CdIn_2S_4$ single crystal thin films was found to be $E_g(T)\;=\;2.7116\;eV\;-\;(7.74{\times}10^{-4}\;eV)T^2/(T+434)$. After the as-grown $CdIn_2S_4$ single crystal thin films was annealed in Cd-, S-, and In-atmospheres, the origin of point defects of $CdIn_2S_4$ single crystal thin films has been investigated by the photoluminescence(PL) at 10 K.

• Proceedings of the IEEK Conference
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• 1999.06a
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• pp.283-286
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• 1999

Transparent conductive aluminum-doped ZnO(AZO) films Were prepared by a ultrasonic spray pyrolysis method at the substrate temperature below 23$0^{\circ}C$. A vertical type hot wall furnace was used as a reactor in the deposition system. Zinc acetate dissolved in methanol was selected as a precursor. The substrate temperature was varied from 18$0^{\circ}C$to 24$0^{\circ}C$. Aluminum (Al) was doped into ZnO films by incorporating anhydrous aluminum chloride (AlCl$_3$) in the zinc acetate solution. The proportion of the Al in the starting solution was varied from 0 wt % to 3.0 wt %. The crystallographic properties and surface morphologies of the films were analyzed by X-ray diffraction (XRD) and scanning electron microscopy (SEM), respectively. The resistivity of the films was measured by the Van der Pauw method, and the mobility and carrier concentration were obtained through the Hall effect measurements Transmittance was measured in the visible region. The effects of substrate temperature and aluminum content in the starling solution on the structural and electrical properties of the AZO films are discussed

• JSTS:Journal of Semiconductor Technology and Science
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• v.1 no.3
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• pp.158-166
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• 2001

Based on uniform hot carrier injection (optically assisted electron injection) across the $Si-SiO_2$ interface into the gate insulator of n-channel IGFETs, the threshold voltage shifts associated with electron injection of $1.25{\times}l0^{16}{\;}e/\textrm{cm}^2 between 0.5 and 7 MV/cm were found to decrease from positive to negative values, indicating both a decrease in trap cross section ($E_{ox}{\geq}1.5 MV/cm$) and the generation of FPC $E_{ox}{\geq}5{\;}MV/cm$). It was also found that FNC and large cross section NETs were generated for $E_{ox}{\geq}5{\;}MV/cm$. Continuous, uniform low-field (1MV/cm) electron injection up to $l0^{19}{\;}e/\textrm{cm}^2 is accompanied by a monatomic increase in threshold voltage. It was found that the data could be modeled more effectively by assuming that most of the threshold voltage shift could be ascribed to generated bulk defects which are generated and filled, or more likely, generated in a charged state. The injection method and conditions used in terms of injection fluence, injection density, and temperature, can have a dramatic impact on what is measured, and may have important implications on accelerated lifetime measurements.

• Journal of the Institute of Electronics Engineers of Korea SD
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• v.37 no.6
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• pp.1-8
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• 2000

In this paper, design of sense amplifier for a flash memory minimizing bit line disturbance due to common bit line is presented. There is a disturbance problem at output modes by using common bit line, when the external devices access an internal flash memory. This phenomenon is resulted form hot carrier between floating gates and bit lines by thin oxide thickness. To minimize bit line disturbance, lower it line voltage is required and need sense amplifier to detect data existence in lower bit line voltage. Proposed circuits is operated at lower bit line voltage and we fabricated a embedded flash memory MCU using 0.6u technology.

• JSTS:Journal of Semiconductor Technology and Science
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• v.7 no.2
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• pp.120-131
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• 2007

A comprehensive short channel analytical model has been proposed for High Electron Mobility Transistor (HEMT) to obtain higher cut-off frequency maintaining the reliability of the device. The model has been proposed to consider generalized doping variation in the directions perpendicular to and along the channel. The effect of field plates and different gate-insulator geometry (T-gate, etc) have been considered by dividing the area between gate and the high band gap semiconductor into different regions along the channel having different insulator and metal combinations of different thicknesses and work function with the possibility that metal is in direct contact with the high band gap semiconductor. The variation obtained by gate-insulator geometry and field plates in the field and channel potential can be produced by varying doping concentration, metal work-function and gate-stack structures along the channel. The results so obtained for normal device structure have been compared with previous proposed model and numerical method (finite difference method) to prove the validity of the model.

• JSTS:Journal of Semiconductor Technology and Science
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• v.15 no.6
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• pp.585-593
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• 2015

In the nanoscale regime, many multigate devices are explored to reduce their size further and to enhance their performance. In this paper, design of a novel device called, Triple Material Surrounding Gate Tunnel Field effect transistor (TMSGTFET) has been developed and proposed. The advantages of surrounding gate and tunnel FET are combined to form a new structure. The gate material surrounding the device is replaced by three gate materials of different work functions in order to curb the short channel effects. A 2-D analytical modeling of the surface potential, lateral electric field, vertical electric field and drain current of the device is done, and the results are discussed. A step up potential profile is obtained which screens the drain potential, thus reducing the drain control over the channel. This results in appreciable diminishing of short channel effects and hot carrier effects. The proposed model also shows improved ON current. The excellent device characteristics predicted by the model are validated using TCAD simulation, thus ensuring the accuracy of our model.