• The Transactions of the Korea Information Processing Society
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• v.7 no.9
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• pp.2827-2835
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• 2000

In recent years, much attention has been focused on improving I/O devices' processing speed which is essential in such large data processing areas as multimedia data processing. And studies on high-performance parallel file systems are considered to be one of such efforts. In this paper, an efficient disk allocation scheme is proposed for high-performance parallel file systems. In other words, the concept of a parallel disk file's parallelism is defined using data declustering characteristic of a given parallel file. With the concept, an efficient disk allocation scheme is proposed which calculates the appropriate degree of data declustering on disks for each parallel file in order to obtain the maximum throughput when more than one parallel file is used at the same time. Since, calculation for obtaining the maximum throughput is too complex as the number of parallel files increases, an approximate disk allocation algorithm is also proposed in this paper. The approximate algorithm is very simple and especially provides very good results when I/O workload is high. In addition, it has shown that the approximate algorithm provides the optimal disk allocation for the maximum throughput when the arrival rate of I/O requests is infinite.

• Journal of the Institute of Electronics and Information Engineers
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• v.51 no.4
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• pp.49-58
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• 2014

A low-swing differential near-ground signaling (NGS) transceiver for low-power high-speed mobile I/O interface is presented. The proposed transmitter adopts an on-chip regulated programmable-swing voltage-mode driver and a pre-driver with asymmetric rising/falling time. The proposed receiver utilizes a new multiple gain-path differential amplifier with feed-forward capacitors that boost high-frequency gain. Also, the receiver incorporates a new adaptive bias generator to compensate the input common-mode variation due to the variable output swing of the transmitter and to minimize the current mismatch of the receiver's input stage amplifier. The use of the new simple and effective impedance matching techniques applied in the transmitter and receiver results in good signal integrity and high power efficiency. The proposed transceiver designed in a 65-nm CMOS technology achieves a data rate of 13 Gbps/channel and 0.3 pJ/bit (= 0.3 mW/Gbps) high power efficiency over a 10 cm FR4 printed circuit board.

• Journal of Korea Multimedia Society
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• v.15 no.12
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• pp.1499-1505
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• 2012

Recently, the distributed processing system for big data has been actively investigated owing to the development of high speed network and storage technologies. In addition, virtual system that can provide efficient use of system resources through the consolidation of servers has been increasingly recognized. But, when we configure distributed processing system for big data in virtual machine environments, many problems occur. In this paper, we did an experiment on the optimization of I/O bandwidth according to the creation and placement of VMs and tasks with composing Hadoop cluster in virtual environments and evaluated the results of an experiment. These results conducted by this paper will be used in the study on the development of Hadoop Scheduler supporting I/O bandwidth balancing in virtual environments.

• 제어로봇시스템학회:학술대회논문집
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• 1997.10a
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• pp.672-675
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• 1997

This paper proposes a structure of the control system for the step & scan exposure tool. The step & scan exposure tool is used for the manufacturing process of the semiconductor DRAM memory of giga bit. The control system employs the VME bus instead of the conventional ISA bus so that all control signals and data can be managed separately by the 4 VME-PCs for fast and fault-free flow of signals for multi-tasking. A high speed I/O card is equipped for the real-time monitoring and control of the sub module equipment. Then all the subsystems are integrated and aligned for the operation of the step & scan exposure tool with the VME bus and, I/O card.

• Proceedings of the IEEK Conference
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• 2005.11a
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• pp.805-808
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• 2005

In this study, the design of advanced LVDS(Low Voltage Differential Signaling) I/O interface circuit with new structural low triggering ESD(Electro-Static Discharge) protection circuit was investigated. Due to the differential transmission technique and low power consumption at same time. maximum transmission data ratio of designed LVDS transmitter was simulated to 5Gbps, Also, the LIGCSCR(Latch-up Immune Gate Coupled SCR)was designed. It consists of PLVTSCR (P-type Low Voltage Trigger SCR), control NMOS and RC network. The triggering voltage was simulated to 3.6V. And the latch-up characteristics were improved. Finally, we performed the layout high speed I/O interlace circuit with the low triggered ESD protection device in one-chip.

• JSTS:Journal of Semiconductor Technology and Science
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• v.9 no.4
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• pp.198-204
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• 2009

Inductive peaking using T-coils has been widely used in broadband I/O interfaces. In this paper, we analyze technical effects and limitations of the T-coil, and discuss several methods that can overcome these restrictions and improve the practicality of the T-coil. In particular we also propose and verify a circuit topology which can further extend bandwidth beyond the limit that conventional T-coil can achieve, and transfer 20 Gb/s data without noticeable distortion.

• Journal of the Korean Institute of Telematics and Electronics
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• v.24 no.6
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• pp.1040-1048
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• 1987

We propose a hardware architecture called Multiring which is applicable for various geometrical operations on rectilinear objects such as design rule checking in VLSI layout and many image processing operations including noise suppression and coutour extraction. It has both a fast execution speed and extremely high flexibility. The whole architecture is mainly divided into four parts` I/O between host and Multiring, ring memory, linear processor array and instruction decoder. Data transmission between host and Multiring is bit serial thereby reducing the bandwidth requirement for teh channel and the number of external pins, while each row data in the bit map stored in ring memory is processed in the corresponding processor in full parallelism. Each processor is simultaneously configured by the instruction decoder/controller to perform one of the 16 basic instructions such as Boolean (AND, OR, NOT, and Copy), geometrical(Expand and Shrink), and I/O operations each ring cycle, which gives Multiring maximal flexibility in terms of design rule change or the instruction set enhancement. Correct functional behavior of Multiring was confirmed by successfully running a software simulator having one-to-one structural correspondence to the Multiring hardware.

• Proceedings of the Korean Society for Technology of Plasticity Conference
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• 2005.10a
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• pp.259-264
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• 2005

The shrinkage of the product in injection molded part occurs due to the volume change with variation of temperature and pressure and is influenced by the processing conditions of injection molding. Mold designers greatly concerns the shrinkage of parts for a high dimensional accuracy. In this study, bar type HIPS specimen with 15x19 grid on the surface was tested. The amount of shrinkage of flow and transverse directions was examined with respect to the injection molding conditions such as melt temperature, injection speed, holding pressure, mold temperature and cooling time. As the packing pressure increased, the difference of shrinkage of both directions is decreased and the absolute shrinkage value also decreased.

• Journal of the Korea Academia-Industrial cooperation Society
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• v.14 no.5
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• pp.2449-2456
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• 2013

The column-oriented database storage is a very advanced model for large-volume data analysis systems because of its superior I/O performance. Traditional data storages exploit row-oriented storage where the attributes of a record are placed contiguously in hard disk for fast write operations. However, for search-mostly datawarehouse systems, column-oriented storage has become a more proper model because of its superior read performance. Recently, solid state drive using MLC flash memory is largely recognized as the preferred storage media for high-speed data analysis systems. In this paper, we introduce fast column-oriented data storage model and then propose a new storage management scheme using a cross compressed replication for the high-speed column-oriented datawarehouse system. Our storage management scheme which is based on two MLC SSD achieves superior performance and reliability by the cross replication of the uncompressed segment and the compressed segment under high workloads of CPU and I/O. Based on the results of the performance evaluation, we conclude that our storage management scheme outperforms the traditional scheme in the respect of update throughput and response time of the column segments.

• Journal of the Institute of Electronics Engineers of Korea CI
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• v.41 no.4
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• pp.41-49
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• 2004

In this paper, a design and measurement method for FPGA embedded gigabit-transceiver is presented. Altera's Stratix GX device which is general purpose transceiver called GXB was used for implementing PCI Express transceiver. PCI Express is the generation high performance serial I/O bus used to interconnect peripheral devices. After GXB was set follow by PCI Express specifications, the design has been verified by timing simulation and implemented as hardware. We tested it as follow. First GXB internal digital and analog block test second GXB transmitter signal integrity test called Eye mask test, third GXB high-speed serial I/O buffer and on-chip termination test and the last GXB protocol test. This paper shows all the design and measurement procedure about FPGA embedded gigabit-transceiver.