• The Transactions of the Korea Information Processing Society
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• v.4 no.2
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• pp.499-514
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• 1997

This paper proprses the architeecture of an interconnection network for Advanced Information Communi-cation Procssing System(AICPS)developde for prividing open information communication servies on a variety of heterogeneous networks.The proposed Interconnection network,called High Speed Swiching Fabric(HSSF),has been designed by a common bus.It can handile 32 i/O channels,each of which uses serial communication method using 100Mbps TAXI.The switching bandwidth of the common bus is 640Mvps.Each I/O channel can be alloted about 20Mbps bandwidth in steady state,and therefore it's sufficient bandwidth is able to interwork with ISDN and Internet services, as well as PSTN. HSSF is composed of the switching board assembly,the subscriber,I/O board assemly,and the backplane board assembly.An attached node takes in the network adapter board assembly to adapt the high speed interworking protocol.For reliability,HSSF is duplicated with load-sharing method.

• Journal of Digital Convergence
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• v.12 no.1
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• pp.379-388
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• 2014

We noted that substituting hard disk with high-performance storage device on SAN did not immediately result in getting high performance. Investigating the reason behind this leaded us to propose optimization schemes for high-performance storage system. We first got rid of the latency in the I/O process which is unsuitable for the high-performance storage device, added parallelism on the storage server, and applied temporal merge to Superhigh speed network protocol for improving the performance with small random I/O. The proposed scheme was implemented on the SAN with high-performance storage device and we verified that there were about 30% reduction on the I/O delay latency and 200% improvement on the storage bandwidth.

• Proceedings of the KIEE Conference
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• 2004.11c
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• pp.687-689
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• 2004

As using of network increases rapidly, performance of system has been deteriorating because of the overhead and bottleneck. Nowadays, High speed I/O network standard, that is a sort of PCI Express, HyperTransport, InfiniBand, and so on, has come out to improve the limites of traditional I/O bus. The InfiniBand Architecture(IBA) provides some protocols to service the applications such as SDP, SRP and IPoIB. In our paper, We explain the architecture of IPoIB (IP over InfiniBand) and its features in channel based I/O network. And so we provide a performance evaluation result of IPoIB which is compared with current network protocol. Our experimental results also show that IPoIB is batter than TCP/IP protocol. For this test, We use the dual processor server systems and Linux Redhat 9.0 operating system.

• Proceedings of the KSR Conference
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• 2009.05a
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• pp.1473-1479
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• 2009

Recently, the high speed train was operated and then the train system's reliability requirements are growing more and more. The exact prediction simulation is necessary in the design of power feeding system by the increase of railway electrification. In order to develope the AC feeding system analysis technology, real-time power simulator was manufactured. It is composed to eight channels analog input, forty channels analog output and forty-eight channels digital I/O. The size of simulator rack is 19" and the two I/O boards are installed the PXI chassis built into the real time os. The signal I/O is possible through BNC connector. The test results of manufactured simulator are obtained that the error range of analog I/O signal is below 1 % and simulation condition is set to 1 ms and the simulation output of the analog output compares the results of the simulator.

• Proceedings of the KIEE Conference
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• 2005.07d
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• pp.3034-3036
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• 2005

High speed PC-based digital I/O system, PCI-bus master and slave. set is developed, which features are distributed structure, input/output function interchangeability by switch settings, and high speed(20Mbps). Library and application software for a DIO system that have a secure and a convenient functionality are developed.

• Proceedings of the KIEE Conference
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• 2005.07d
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• pp.3031-3033
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• 2005

High speed PC-based digital I/O system hardware, PCI-bus master and slave set is developed, which features are distributed structure, input/output function interchangeability by switch setting, high speed 20Mbps to update 1000 points in less than 1 ms, etc.

• 한국정보디스플레이학회:학술대회논문집
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• 2007.08a
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• pp.806-809
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• 2007

SRAM cell array and peripheral circuits on display panel are designed using LTPS process. To overcome low yield of SOP, high speed parallel fault detection circuitry for memory cells is designed at local I/O lines with minimal overhead for efficient memory cell redundancy replacement. Normal read/write and parallel test read/write are simulated and verified.

• Journal of the Institute of Electronics Engineers of Korea SD
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• v.43 no.6 s.348
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• pp.9-17
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• 2006

We proposed a new High-speed CMOS Level Up/Down Shifter circuits that can be used with Dynamic Voltage and Frequency Scaling(DVFS) algorithm, for low power system in the SoC(System-on-Chip). This circuit used to interface between the other voltage levels in each CMOS circuit boundary, or between multiple core voltage levels in a system bus. Proposed circuit have advantage that decrease speed attenuation and duty ratio distortion problems for interface. The level up/down shifter of the proposed circuit designed that operated from multi core voltages$(0.6\sim1.6V)$ to used voltage level for each IP at the 500MHz input frequency The proposed circuit supports level up shifting from the input voltage levels, that are standard I/O voltages 1.8V, 2.5V, 3.3V, to multiple core voltage levels in between of $0.6V\sim1.6V$, that are used internally in the system. And level down shifter reverse operated at 1Ghz input frequency for same condition. Simulations results are shown to verify the proposed function by Hspice simulation, with $0.6V\sim1.6V$ CMOS Process, $0.13{\mu}m$ IBM CMOS Process and $0.65{\mu}m$ CMOS model parameters. Moreover, it is researched delay time, power dissipation and duty ration distortion of the output voltage witch is proportional to the operating frequency for the proposed circuit.

• Journal of the Institute of Electronics Engineers of Korea SC
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• v.45 no.2
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• pp.26-36
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• 2008

Due to the differential and low voltage swing, Low Voltage Differential Signaling(LVDS) has been widely used for high speed data transmission with low power consumption. This paper proposes new LVDS I/O interface circuits for more than 1.3 Gb/s operation. The LVDS receiver proposed in this paper utilizes a sense amp for the pre-amp instead of a conventional differential pre-amp. The proposed LVDS allows more than 1.3 Gb/s transmission speed with significantly reduced driver output voltage. Also, in order to further improve the power consumption and noise performance, this paper introduces an inductance impedance matching technique which can eliminate the termination resistor. A new form of unfolded impedance matching method has been developed to accomplish the impedance matching for LVDS receivers with a sense amplifier as well as with a differential amplifier. The proposed LVDS I/O circuits have been extensively simulated using HSPICE based on 0.35um TSMC CMOS technology. The simulation results show improved power gain and transmission rate by ${\sim}12%$ and ${\sim}18%$, respectively.

• Proceedings of the IEEK Conference
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• 2003.07b
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• pp.979-982
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• 2003

Due to the differential transmission technique and low voltage swing, LVDS has been widely used for high speed transmission with low power consumption. This paper presents the design and implementation of interface circuits for 1.5Gb/s operation in 0.35um CMOS technology. The interface circuit ate fully compatible with the low-voltage differential signaling(LVDS) standard. The LVDS proposed in this paper utilizes a sense amplifiers instead of the conventional differential pre-amplifier, which provides a 1.5Gb/s transmission speed with further reduced driver output voltage. Furthermore, the reduced driver output voltage results in reducing the power consumption.