Proceedings of the IEEK Conference (대한전자공학회:학술대회논문집)

The Institute of Electronics and Information Engineers (대한전자공학회)
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1.5Gb/s Low Power LVDS I/O with Sense Amplifier

Sense amplifier를 이용한 1.5Gb/s 저전력 LVDS I/O 설계

  • 변영용 (동국대학교 전자공학과) ;
  • 이승학 (동국대학교 전자공학과) ;
  • 김성하 (동국대학교 전자공학과) ;
  • 김동규 (동국대학교 전자공학과) ;
  • 김삼동 (동국대학교 전자공학과) ;
  • 황인석 (동국대학교 전자공학과)
  • Published : 2003.07.01
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Abstract

Due to the differential transmission technique and low voltage swing, LVDS has been widely used for high speed transmission with low power consumption. This paper presents the design and implementation of interface circuits for 1.5Gb/s operation in 0.35um CMOS technology. The interface circuit ate fully compatible with the low-voltage differential signaling(LVDS) standard. The LVDS proposed in this paper utilizes a sense amplifiers instead of the conventional differential pre-amplifier, which provides a 1.5Gb/s transmission speed with further reduced driver output voltage. Furthermore, the reduced driver output voltage results in reducing the power consumption.

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